Development of the self-aligned titanium silicide process for VLSI applications

Alperin, M.E.; Holloway, T.C.; Haken, R.A.; Gosmeyer, C.D.; Karnaugh, R.; Parmantie, W.D.

doi:10.1109/t-ed.1985.21923

Cited by 138 publications

(19 citation statements)

References 12 publications

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“…However, such a stringent alignment accuracy cannot be met by current photolithography tools, nor can be achieved by conventional symmetrical self-alignment of the source and drain with the gate. [8][9][10] To overcome this alignment challenge, it is preferable to have a reliable self-aligned method to fabricate an asymmetric trench in the source. Previously, self-aligned asymmetric source/drain doping was achieved in different FET structures by combining a vertical and a tilted implant 11 or using a sidewall-spacer gate; 2,6 but in these methods, the source/ drain substrate materials still remained the same and no asymmetric trenches were created.…”

Section: Introductionmentioning

confidence: 99%

Self-aligned fabrication of 10 nm wide asymmetric trenches for Si/SiGe heterojunction tunneling field effect transistors using nanoimprint lithography, shadow evaporation, and etching

Wang

Chou

2009

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Fabrication of an asymmetric source/drain structure is important to heterojunction tunneling transistors but is extremely difficult to achieve reliably due to the stringent requirement of nanometer overlay alignment. Here the authors propose and demonstrate a simple self-aligned asymmetric nanotrench fabrication method, which has achieved a 10 nm wide (35 nm deep) trench in source region with an alignment accuracy better than 3 nm. The method is based on asymmetric shadow evaporation of the metal with the gate as a mask, creating an area uncovered by the metal only in the source but not in the drain, and a subsequent reactive ion etching with the evaporated metal as the etching mask. The accuracy of this method was found experimentally and theoretically to be within 5 nm.

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Section: Introductionmentioning

confidence: 99%

Self-aligned fabrication of 10 nm wide asymmetric trenches for Si/SiGe heterojunction tunneling field effect transistors using nanoimprint lithography, shadow evaporation, and etching

Wang

Chou

2009

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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“…A SHALLOW junction with a self-aligned silicide (salicide) structure has been widely studied for improving deep submicron device performance [1], [2]. Previously, excellent silicided shallow junctions have been formed by implanting dopant into thin metal or silicide layer and subsequent annealing [3]- [5].…”

Section: Introductionmentioning

confidence: 99%

Various effects of silicidation on shallow p/sup +/ junctions formed by BF/sub 2//sup +/ implantation into thin poly-Si films on Si substrates

Juang

1999

IEEE Electron Device Lett.

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Various effects of silicidation on shallow p + n junctions formed by the scheme that implants BF + 2 ions into thin poly-Si films on Si substrates are described. A post-Ni silicidation just slightly improves the preformed junctions of the annealed sample. However, as the sample is first deposited with thin Ni films after the implantation and then annealed, the resulting junctions are much better than the preformed ones. Moreover, as the sample is deposited with Ti films, the resultant junctions are just slightly better the preformed ones.

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“…Likewise, the shrinking feature size and circuit packing density heighten the sensitivity of performance to the resistivity of circuit conductors and the dielectric constants of associated insulators. This has led to an increase in the use of silicides with resistivity inherently superior to that of degenerately doped silicon in order to alleviate the resistance increase associated with reduced feature size [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

Silicides and local interconnections for high-performance VLSI applications

Mann

Clevenger

Agnello³

et al. 1995

IBM J. Res. & Dev.

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As the minimum VLSI feature size continues to scaie down to the 0.1-0.2-ju.m regime, the need for iow-resistance iocai interconnections wiii become increasingiy critical. Although reduction in the MOSFET channel length will remain the dominant factor in achieving higher circuit performance, existing local interconnection materials will impose greater than acceptable performance limitations. We review the state-of-the-art salicide and polycide processes, with emphasis on work at IBM, and discuss the limitations that pertain to future implementations in high-performance VLSI circuit applications. A brief review of various silicide-based and tungsten-based approaches for forming local interconnections is presented, along with a more detailed description of a tungsten-based "damascene" local interconnection approach.

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Development of the self-aligned titanium silicide process for VLSI applications

Cited by 138 publications

References 12 publications

Self-aligned fabrication of 10 nm wide asymmetric trenches for Si/SiGe heterojunction tunneling field effect transistors using nanoimprint lithography, shadow evaporation, and etching

Self-aligned fabrication of 10 nm wide asymmetric trenches for Si/SiGe heterojunction tunneling field effect transistors using nanoimprint lithography, shadow evaporation, and etching

Various effects of silicidation on shallow p/sup +/ junctions formed by BF/sub 2//sup +/ implantation into thin poly-Si films on Si substrates

Silicides and local interconnections for high-performance VLSI applications

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