Developments in Si and SiO 2 etching for MEMS-based optical applications

Donohue, L.A.; Hopkins, Janet; Barnett, Richard; Newton, Andrew; Barker, A.

doi:10.1117/12.524471

Cited by 21 publications

(16 citation statements)

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“…The second approach to reduce the PR erosion effect is to use other RIE techniques that provide better selectivity to photoresist. For example, an Surface Technology Systems (STS) Advanced Oxided Etcher system provides more than 10 : 1 selectivity and 89 • etch angle with an oxide etch rate between 0.3 and 0.5 µm/min, which results in a better etching profile for this step [20].…”

Section: Fabrication and Discussionmentioning

confidence: 99%

Low-Mass PECVD Oxynitride Gas Chromatographic Columns

Agah

Wise

2007

J. Microelectromech. Syst.

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This paper describes the realization of low-power micro gas chromatography columns for portable gas analysis systems. The columns are fabricated using complimentary metal-oxide-semiconductor-compatible buried-channel plasmaenhanced chemical vapor deposition oxynitride films that have nearly zero stress at room temperature, high deposition rate (∼1 µm/min), high etch rate selectivity (∼1:80), low thermal conductivity (< 5 W/m • C), and low thermal stress (< 140 kPa/ • C). The buried channel process utilizes these films to form 25-cm-long 65-µm-ID semicircular columns on a 6-mm-square chip. With more than 5000 theoretical plates, these columns separate multicomponent gas mixtures with performance comparable to that of commercial fused silica capillary columns. The columns are capable of multisecond analyses when integrated with low-deadvolume injectors and dissipate less than 10 mW at 150 • C in vacuum.[ 2006-0208]Index Terms-Buried channel, complimentary metal-oxidesemiconductor (CMOS) compatible, micro gas chromatography (GC), microelectromechanical systems (MEMS), separation column, silicon oxynitride (SiON).

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Section: Fabrication and Discussionmentioning

confidence: 99%

Low-Mass PECVD Oxynitride Gas Chromatographic Columns

Agah

Wise

2007

J. Microelectromech. Syst.

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“…В эпитаксиальном слое 7 диффузией или эпитакси-ей формируется область p-типа 4. Таким образом, получается диодная структура с p-n-переходом, со-стоящая из слоев 4, 7,8. Для того чтобы при обратном смещении не было пробоя по перимет-ру диодной структуры, на рисунке приведен ва-риант расширения области пространственного за-ряда с помощью охранного кольца 9.…”

Section: анализ принципа действия моп-транзисторовunclassified

Specifics of Silicon Deep Anisotropic Etching in Trench MOSFET Manufacturing Technology

Anurov¹,

Zabotin²,

Podgorodetsky³

2015

Rocket-Space Device Engineering and Information Systems

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Аннотация. В докладе рассмотрены особенности травления тренчей для формирования затвора в технологии изготовления вертикальных силовых МОП-транзисторов и представлены зависимости геометрии тренчей от па-раметров травления. Показано, что пропорциональное изменение расходов газов не оказывает существенного влияния на режим травления и вид тренчей, а соотношение времени травления и осаждения пассивации сильно влияет на наклон стенок тренча и шероховатость дна. Abstract. Operation of gate trench etching for vertical power MOSFET manufacturing technology is considered and investigation results are shown as dependences of trench geometry from etch parameters and as parameters of the final etch regime in this paper. It is shown that gas flows' proportional change has a little effect on the etch regime and the trench form, and etch time to deposition time ratio has a strong influence on the wall slope and the bottom roughness.

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“…1(e). For example, fused silica on silicon wafers are commercially available for such endeavors, and advanced oxide etching of a BOX layer through a silicon via hole has been demonstrated [9]. …”

Section: Problem Statement and Main Ideamentioning

confidence: 99%

CMUT fabrication based on a thick buried oxide layer

Kupnik

Vaithilingam

Torashima

et al. 2010

2010 IEEE International Ultrasonics Symposium

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We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required -in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate.

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Developments in Si and SiO 2 etching for MEMS-based optical applications

Cited by 21 publications

References 0 publications

Low-Mass PECVD Oxynitride Gas Chromatographic Columns

Low-Mass PECVD Oxynitride Gas Chromatographic Columns

Specifics of Silicon Deep Anisotropic Etching in Trench MOSFET Manufacturing Technology

CMUT fabrication based on a thick buried oxide layer

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