Device and circuit performance of Si-based accumulation-mode CGAA CMOS inverter

Panda, Soumya Ranjan; Pradhan, K P; Sahu, Prasanna Kumar

doi:10.1016/j.mssp.2017.04.005

Cited by 10 publications

(6 citation statements)

References 19 publications

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“…Table V shows the comparative analysis of CMOS inverter at optimized value with the previous literatures. Propagation delay is observed lesser for proposed device as compared to Celik et al, 19 Rodoni et al 20 and Panda et al 21 However, noise margin is lesser for proposed device which can be trade-off with the propagation delay.…”

Section: Cmos Inverter-in the Digital Circuit Design Cmos Inverter Ismentioning

confidence: 68%

Design of High Speed and Low-Power Ring Oscillator Circuit in Recessed Source/Drain SOI Technology

Priya

Srivastava

Mishra

2019

ECS J. Solid State Sci. Technol.

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In this paper, switching speed of CMOS inverter and Ring Oscillator is analyzed for the first time using Triple-Metal-Gate (TMG) Recessed-Source/Drain (Re-S/D) SOI MOSFET. Re-S/D SOI MOSFET has the capability to reduce the series resistance of the device due to the extended depth of source and drain into buried oxide layer. So the current drive capability of this device is improved which in turn improves the input/output switching in the inverter and ring oscillator. In this paper, transfer characteristics, delay and frequency is analyzed for inverter as well as for ring oscillator with TMG Re-S/D SOI MOSFET. DC and transient analysis such as transfer characteristics, noise margin, power dissipation, delay, and frequency is done for CMOS inverter and ring oscillator. Also, the Voltage Transfer Characteristic (VTC) has been compared with the available SMG and DMG structures of Re-S/D FD SOI MOSFET for the analysis switching behavior. This DC and transient simulation are performed using 2-dimensional numerical TCAD simulator ATLAS from Silvaco.

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Section: Cmos Inverter-in the Digital Circuit Design Cmos Inverter Ismentioning

confidence: 68%

Design of High Speed and Low-Power Ring Oscillator Circuit in Recessed Source/Drain SOI Technology

Priya

Srivastava

Mishra

2019

ECS J. Solid State Sci. Technol.

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“…8). 32 As discussed previously, Inverter based on the Si model has superior voltage transfer characteristics than the inverter based on the hybrid model. The switching characteristics of the JL-DG-MOSFET-based inverter circuit for Si and the suggested hybrid model are shown in Fig.…”

Section: Results Analysismentioning

confidence: 88%

“…The Si-based CMOS inverter exhibits a sharp transition in VTC, indicating a larger voltage gain (dV out /dV in ). The intersection point of VTC where V in and V out are equal is known as the inverter's threshold voltage, 32 which is almost half of V dd . When one inverter's output is sent to the next inverter through an interconnect, the interconnects are extremely vulnerable to noise.…”

Section: Results Analysismentioning

confidence: 99%

“…As a result, there is a potential that the original signal will be disrupted. This is indicated as noise margin (NM), 32 a critical metric for defining the circuit's noise immunity. 20 Two noise margins are specified based on the logic level.…”

Section: Results Analysismentioning

confidence: 99%

“…20 Two noise margins are specified based on the logic level. VTC is used to calculate the noise margins NM H and NM L [32][33][34] The noise margins for logic high output (NM H ) and logic low output (NM L ) for both inverters are extracted from the VTC curve (Fig. 8).…”

Section: Results Analysismentioning

confidence: 99%

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Improvement in the Performance of III-V Channel Based Ultra-Thin Junction-Less-Hybrid CMOS Circuits with Mixed Mode Analysis

Rout

Dutta

Maity

2022

ECS J. Solid State Sci. Technol.

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The logic performance of a hybrid complementary-metal-oxide-semiconductor (CMOS) circuit based on a novel technology known as a junction-less transistor constructed with high-K and III-V compound material junction-less-double-gate MOSFET (JL-DG-MOSFET) for ultra-low power applications is analyzed. The CMOS circuit is constructed by using a Ge-based P-MOS and GaAs based N-MOS to analyze different performance metrics of inverter such as noise margin, voltage transfer characteristics, transient response, gain, frequency response, and propagation delay using mixed mode analysis. The aforementioned characteristics of the proposed inverter are analyzed and compared with an Si-based CMOS inverter and we observed that the proposed structure shows an improved circuit performance over Si-based CMOS circuit. Consequently, the work is also extended to the design and performances of universal logic gates. The aforementioned N-MOS structure has a higher drive current of 1.3 mA, gm of 5.9 mS, gd of 20.8 mS, SS of 64 mV/Decade, and DIBL of 23mV/V, whereas the Ge based P-MOS structure yields drive current of 0.7 mA, gm of 1.5 mS, gd of 5.6 mS, SS of 95 mV/Decade, and DIBL of 21mV/V. The hybrid C-MOS structure has a higher unity-gain bandwidth of 1100GHz and lower propagation delay of 3.1ps

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Design and analysis of nano-scaled SOI MOSFET-based ring oscillator circuit for high density ICs

2019

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Device and circuit performance of Si-based accumulation-mode CGAA CMOS inverter

Cited by 10 publications

References 19 publications

Design of High Speed and Low-Power Ring Oscillator Circuit in Recessed Source/Drain SOI Technology

Design of High Speed and Low-Power Ring Oscillator Circuit in Recessed Source/Drain SOI Technology

Improvement in the Performance of III-V Channel Based Ultra-Thin Junction-Less-Hybrid CMOS Circuits with Mixed Mode Analysis

Design and analysis of nano-scaled SOI MOSFET-based ring oscillator circuit for high density ICs

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