Device optimization of the FinFET having an isolated n+/p+ strapped gate

Simulation of Nanoscale Two-Bit Not-And-type Silicon–Oxide–Nitride–Oxide–Silicon Nonvolatile Memory Devices with a Separated Double-Gate Fin Field Effect Transistor Structure Containing Different Tunneling Oxide Thicknesses

“…9,10) However, the electrical properties of scaled-down conventional NVM devices have serious problems due to the short channel effect (SCE), tunneling effect or leakage current at the oxide/ silicon heterointerface, and the coupling capacitance between cells. 11) Fin field effect transistor (FinFET) structures have emerged as excellent candidates for applications in next-generation NVM devices because of their good SCE immunity, high read current, and high punch-through margin. 12,13) NVM devices with a double-gate structure have been studied in order to achieve high performance and low power consumption.…”