Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains

Li, J.C.-M.

doi:10.1109/tc.2005.182

Cited by 35 publications

(13 citation statements)

References 8 publications

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“…1-2-5-8-10 b9 b8 b7 b4 b6 b5 b3 b2 b1 10 1-3-7-9-10 b10 b8 b9 b4 b6 b5 b7 b2 b3 b1 (r1) 11 1-2-4-8-10 b11 b10 b9 b8 b6 b5 b7 b4 b3 b2 (r2) 12 1-3-6-9-10 b12 b10 b11 b8 b6 b9 b7 b4 b5 b3 (r3) 13 1-2-5-8-10 b12 b11 b8 b10 b9 b7 b6 b5 b4 (r4) 14 1-3-7-9-10 b12 b8 b10 b9 b11 b6 b7 b5 (r5) 15 1-2-4-8-10 b12 b10 b9 b11 b8 b7 b6 (r6) 16 1-3-6-9-10 b12 b10 b11 b8 b9 b7 (r7) 17 1-2-5-8-10 b12 b11 b10 b9 b8 (r8) 18 1-3-7-9-10 b12 b10 b11 b9 (r9) 19 1-2-4-8-10 b12 b11 b10 (r10) 20…”

Section: B Fault Modelmentioning

confidence: 99%

“…Software-based methods algorithmically analyze the test data for diagnosis. These can be further broken down into two broad sub-categories: (1) simulation based in which available test patterns are fault simulated and analyzed [2,4,12], and (2) deterministic diagnostic pattern generation (DDPG) based which target individual scan cells on a faulty scan chain for test generation [13,15].…”

Section: Introductionmentioning

confidence: 99%

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Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects

Chen

Seth

Xiang

et al. 2011

2011 Asian Test Symposium

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-We present a combined hardware-software based approach to scan-chain diagnosis, when the outcome of a test may be affected by system faults occurring in the logic outside of the scan chain. For the hardware component we adopt the double-tree scan (DTS) chain architecture, which has previously been shown to be effective in reducing power, volume, and application time of tests for stuck-at and delay faults. We develop a version of flush test which can resolve a multiple fault in a DTS chain to a small number of suspect candidates. Further resolution to a unique multiple fault is enabled by the software component comprising of fault simulation and analysis of the response of the circuit to test patterns produced by ATPG. Experimental results on benchmark circuits show that near-perfect scan-chain diagnosis for multiple faults is possible even when a large number of random system faults are injected in the circuit.

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Section: B Fault Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects

Chen

Seth

Xiang

et al. 2011

2011 Asian Test Symposium

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“…Several techniques for diagnosis of hold time failures in scan chains [3][4][5][6] as well as in generic short logic paths [7] are proposed. These techniques are applied for buffer insertion, i.e.…”

Section: Introductionmentioning

confidence: 99%

Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.

Neuberger¹,

Wirth²,

Kastensmidt³

et al. 2009

VLSI-SoC: Advanced Topics on Systems on a Chip

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Abstract. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we investigate the variability of flip-flop race immunity in 130nm and 90nm low power CMOS technologies. An on-chip measurement technique with resolution of ~1ps is used to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Statistical die-to-die variations of hold time violations are measured in various register-to-register configurations and show overall 3σ die-to-die standard deviations of 12-16%. Mathematical methods to separate the measured variability between systematic and random variability are discussed, and the results presented. They show that while systematic variability is the major issue in 130nm, it is significantly decreased in 90nm technology due to better process control. Another important point is that the race immunity decreases about 30% in 90nm, showing that smaller clock skews can lead to violations in 90nm. Normality tests to check if the variability follows a normal Gaussian distribution are also presented.

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“…Faulty scan chains are easily determined by what are called flush tests [13,17]. Thus the goal of scan chain failure diagnosis methods is to locate the scan cells that are faulty in a known faulty scan chain.…”

Section: Introductionmentioning

confidence: 99%

“…They are usually effective but require special scan chain designs with extra hardware overhead. Software-based techniques [10][11][12][13][14][15][16][17][18][19][20][21][22] use diagnosis algorithms to identify faulty scan cells and do not require modification of the conventional scan design, which makes them widely and easily adopted.…”

Section: Introductionmentioning

confidence: 99%

On Improving Diagnostic Test Generation for Scan Chain Failures

Tang

Guo

Cheng

et al. 2009

2009 Asian Test Symposium

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In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-cycle scan test patterns. A diagnostic test generation flow to speed up diagnosis is proposed to address the issue of long run times of test generation and large number of test patterns for the cases where the range of suspected cells is large. Experimental results on several industrial designs show the effectiveness of the proposed procedures in improving diagnostic resolution, reducing run times of test generation and also reducing the number of test patterns.

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Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains

Cited by 35 publications

References 8 publications

Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects

Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects

Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.

On Improving Diagnostic Test Generation for Scan Chain Failures

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