Different Approaches for Clock Skew Analysis in Present and Future Synchronous IC's

Tosik, G.; Gallego, L.M.S.; Lisik, Zbigniew

doi:10.1109/eurcon.2007.4400541

Cited by 5 publications

(3 citation statements)

References 14 publications

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“…A common pairing would be a global H-tree followed by a local mesh [27], minimizing the clock skew in the network and the power consumption of the mesh. Typically, the global distribution can be constructed using a mesh or tree, and the local network can use a tree, mesh or fishbone structure [13].…”

Section: ) Resonant Clockingmentioning

confidence: 99%

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

Chattopadhyay

Žilić

2012

IEEE Trans. VLSI Syst.

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We present a clock distribution network that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modular, standard cell-based design approach that mitigates the effect of intra-die temperature and process variances. We route the clock line serially, using an averaging technique to eliminate skew between clock regions in a domain. Routing clock lines serially allows optimal wire usage for clock networks by eliminating the redundant wires required to match path delays. Our clock network provides control over regional clock skews, can be used in beneficial skew applications and facilitates silicon-debug. Serial clocking permits the use of routing switches in the clock network and allows post-silicon resizing and reshaping of clock domains. Defective sections of the clock network can be bypassed, providing post silicon repair capability. The system uses a closed-loop synchronization phase to combine the clock skew reduction of an actively synchronized clock network with an open-loop operating phase that minimizes power consumption like passive clock networks. Our clock network provides significant flexibility for application-specific integrated circuit, system-on-chip, and field-programmable gate-array designs, exhibiting good operating characteristics everywhere in the design envelope. Our silicon implementation achieves a maximum edge-to-edge uncertainty of 80 ps for regional clocks, which is roughly equal to the cycle-to-cycle jitter of the on-chip clock source.

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Section: ) Resonant Clockingmentioning

confidence: 99%

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

Chattopadhyay

Žilić

2012

IEEE Trans. VLSI Syst.

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“…2 Clock skew uncertainty: As technology scales, the effect of process variations on clock skew is aggravated [14], [15]. Clock skew can be modeled as composed of both deterministic and probabilistic elements [13], [18].…”

Section: Skew Constraints and Uncertaintymentioning

confidence: 99%

“…These networks are composed of a large number of mesh nodes and unbalanced loads, making these networks difficult to analyze, optimize, and automate [6], [12], [13]. Routing redundancies require significant resources as compared to optimized tree-based clock distribution networks where point-topoint routing is used [7].…”

Section: Introductionmentioning

confidence: 99%

Timing-driven variation-aware nonuniform clock mesh synthesis

Abdelhadi

Ginosar

Kolodny

et al. 2010

Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI

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Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. However, these networks incur an increase in dissipated power while consuming significant metal resources. Several methods have been proposed to trade off power and wires to reduce skew. In this paper, an efficient algorithm is presented to reduce skew variations rather than skew, and prioritize the algorithm for critical timing paths, since these paths are more sensitive to skew variations. The algorithm has been implemented for a standard 65 nm cell library using standard EDA tools, and has been tested on several benchmark circuits. As compared to other methods, experimental results show a 37% average reduction in metal consumption and 39% average reduction in power dissipation, while insignificantly increasing the maximum skew.

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Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks

et al. 2013

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Different Approaches for Clock Skew Analysis in Present and Future Synchronous IC's

Cited by 5 publications

References 14 publications

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

Timing-driven variation-aware nonuniform clock mesh synthesis

Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks

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