Different mechanism to explain the 1∕f noise in n- and p-SOI-MOS transistors fabricated on (110) and (100) silicon-oriented wafers

Gaubert, Philippe; Teramoto, Akinobu; Cheng, Wei; Hamada, T.; Ohmi, Tadahiro

doi:10.1116/1.3054280

Cited by 13 publications

(6 citation statements)

References 49 publications

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“…The transistor fabricated on the Si(100) wafer generates the least noise. This finding is consistent with the results found in the literature and reflects the extremely well adapted processes for Si(100) wafers and the high integrity of the Si=SiO 2 interface 47) fabricated on silicon (100) surfaces compared with that fabricated on silicon (110) surfaces. Even if accumulation-mode p-MOSFETs on Si(110) wafers have the highest noise level, their noise is quite comparable to that stemming from inversion-mode p-MOSFETs on Si(110) wafers.…”

Section: Noise Characteristicssupporting

confidence: 92%

Performances of accumulation-mode n- and p-MOSFETs on Si(110) wafers

Gaubert

Teramoto

Sugawa

2017

Jpn. J. Appl. Phys.

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In this study, we investigate the electrical and noise performances of accumulation-mode n- and p-MOSFETs on Si(110) wafers and compare them with conventional MOSFETs fabricated either on Si(100) or Si(110) wafers. With regard to electrical performances, accumulation-mode p-type MOSFETs are in every aspect superior. However, its n-type counterpart does not provide the best performances even though they are still superior to conventional transistors when fabricated on the same type of wafer. Conventional inversion-mode n-MOSFETs on Si(100) wafers still display the best performances. The simultaneous improvement and reduction in drivability respectively in the p- and n-type transistors make the accumulation-mode MOSFETs fabricated on Si(110) wafers extremely well suited for complementary technologies owing to their great balance in terms of drivability. With regard to noise evaluation, accumulation-mode MOSFETs on Si(110) wafers exhibit the highest noise level even though they compare relatively well with the inversion transistors on Si(110) wafers, especially for p-type ones. The lowest noise level is obtained for conventional inversion-mode MOSFETs on Si(100) wafers, and the type of wafer upon which transistors are fabricated is the reason. Indeed, the fabrication of high-quality Si/SiO2 interfaces is better achieved for silicon wafers with a (100) crystallographic orientation, leading to few interface defects and consequently less noise.

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Section: Noise Characteristicssupporting

confidence: 92%

Performances of accumulation-mode n- and p-MOSFETs on Si(110) wafers

Gaubert

Teramoto

Sugawa

2017

Jpn. J. Appl. Phys.

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“…Nevertheless, the method proposed by Tsividis has been used for the Si(110) p-MOSFETs while the Ciofi and Ghibaudo method helped extract the conduction parameters for the Si(110) n-MOSFETs. The results are reported in a previous paper by Gaubert et al [32]. The mobility in Si(110) p-MOSFETs is shown in Figure 10.…”

Section: Silicon Wafers With a (110) Crystallographic Orientationsupporting

confidence: 73%

“…From Ref. [32], the value of the attenuation factor θ for the Si(100) Figure 10. Effective mobility μ eff as a function of the effective electric field E eff for Si(110) p-MOSFETs featuring a channel along several directions.…”

Section: Silicon Wafers With a (110) Crystallographic Orientationmentioning

confidence: 99%

“…The low field mobility μ 0 , the mobility attenuation factor θ, the gate length reduction ΔL, the gate width reduction ΔW and the parasitic access resistances R acc have been extracted for Si (100) n-and p-MOSFETs and are available in a previous paper by Gaubert et al [32]. The Ghibaudo and Ciofi methods have been used.…”

Section: Silicon Wafers With a (100) Crystallographic Orientationmentioning

confidence: 99%

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Carrier Mobility in Field-Effect Transistors

Gaubert¹,

Teramoto²

2017

Different Types of Field-Effect Transistors - Theory and Applications

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Authors investigate the carrier mobility in field-effect transistors mainly when fabricated on Si(110) wafers. They showed that the methods developed to extract the conduction parameters cannot be implemented for Si(110) p-MOSFETs. Authors then developed a more accurate mobility model able to simulate not only the drivability but also the transconductance for these same devices. The study of the relation between the mobility, channel direction and wafer orientation revealed that the channel direction had a significant impact on the mobility for transistors fabricated on Si(110) wafers, the highest electron and hole mobilites being obtained for a channel along the <100> and <110> directions, respectively. No relations were found for Si(100) wafers. The study of the dependence of the scattering mechanism limiting the mobility in Si(110) n-MOSFETs showed that the Coulomb and surface roughness scattering mechanisms were responsible for the degradation of the mobility when compared to the one on Si(100) wafers. Finally, the measurement of the mobility in an accumulation-mode MOSFETs is not straightforward since a bulk contribution, owing to the SOI layer, is adding to channel current. A methodology has been successfully implemented that led to the experimental verification of the universal behaviour of the mobility in an accumulation layer.

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“…Other references included in Fig. 4 are for doped thermistors [27], Si MOSFETs [28][29][30][31] and piezoresistive cantilevers [32]. An explanation of extreme low noise in our system may involve large elastic energy barriers around the P-atom which immobilizes them and reduces the number of active TLSs.…”

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confidence: 99%

Suppression of low-frequency noise in two-dimensional electron gas at degenerately doped Si:Pδlayers

et al. 2011

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We report low-frequency 1/f noise measurements of degenerately doped Si:P δ-layers at 4.2 K. The noise was found to be over six orders of magnitude lower than that of bulk Si:P systems in the metallic regime and is one of the lowest values reported for doped semiconductors. The noise was found to be nearly independent of magnetic field at low fields, indicating negligible contribution from universal conductance fluctuations. Instead interaction of electrons with very few active structural two-level systems may explain the observed noise magnitude.

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Different mechanism to explain the 1∕f noise in n- and p-SOI-MOS transistors fabricated on (110) and (100) silicon-oriented wafers

Cited by 13 publications

References 49 publications

Performances of accumulation-mode n- and p-MOSFETs on Si(110) wafers

Performances of accumulation-mode n- and p-MOSFETs on Si(110) wafers

Carrier Mobility in Field-Effect Transistors

Suppression of low-frequency noise in two-dimensional electron gas at degenerately doped Si:Pδlayers

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