Differentiation of Effects due to Grain and Grain Boundary Traps in Laser Annealed Poly-Si Thin Film Transistors

Abstract

A new physical model based on two dimensional simulations for high quality laser re-crystallised poly-Si thin film transistors is presented. It has been shown that to adequately explain the improved subthreshold slope and the lack of saturation of the output characteristics in these transistors, it is essential to distribute the density of defect states between traps in the grains alongside traps localised at grain boundaries. A double exponential density of states has been extracted for thin film transistors (TFTs) annealed at different excimer laser energies, using the field effect conductance method. By splitting the density of states between grain traps and grain boundary traps good fits to the output characteristics have been achieved. Lack of saturation is shown to be due to decrease in potential barrier at grain boundaries with increase in drain bias. At high gate voltages, however, evidence of a self-heating effect similar to that observed in silicon-on-insulator (SOI) transistors is apparent.

Trapping in organic field-effect transistors

“…However, it has been observed that subthreshold and output characteristic of field-effect transistors are difficult to model in this approximation. 41 Therefore, we would like to assume that the grain boundary has a negligible thickness compared to the grain size L and contains a concentration n t of traps at an energy E t localized at the grain boundary. 42 ͑Similar to the bulk trapping this discrete level may be replaced by a trap distribution.͒ Now, the influence of the grain boundary traps is not only determined by ⌰, more importantly the charge at the grain boundary determines the barrier height E B at the grain.…”

Dependence of polycrystalline silicon thin-film transistor characteristics on the grain-boundary location

“…Although there has been research to analyze the grain-boundary in poly-Si TFTs, [26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41] this article analyzes the dependence on the grain-boundary location, following a brief report by the authors. 42 Figure 1 shows the structure of a poly-Si TFT for twodimensional ͑2D͒ device simulation.…”

Effect of silicon thickness on the degradation mechanisms of sequential laterally solidified polycrystalline silicon TFTs during hot-carrier stress

“…It is generally agreed that for biasstress-induced shifts in poly-Si TFTs, power-law exponents in the range of 0.1-0.3 are indicative of hot-carrier injection, whereas power-law exponents in the range of 0.4-0.6 are indicative of deep-state generation, presumably at crystal-domain boundaries [6], [10], [11]. Accordingly, in this letter we have used the power-law expression shown in (1) to fit the and degradation and extract the value of the exponent " " as a function of film thickness and gate-bias stressing voltage.…”