Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate

Abstract

Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the VDD-VSS admittance that consists of the on-chip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. This paper addresses (1) the dependence of the VDD-VSS admittance on the different states of the circuit and the interconnect and (2) the computation of total supply current with ground bounce. The VDD-VSS admittances of several test circuits are computed with 13% maximum error relative to the measurements on a test ASIC fabricated in a 0.18µm CMOS process on a high-ohmic substrate with 18Ωcm resistivity. It is also shown that this admittance depends on the connectivity of the gates to the supply rail rather than their connectivity among each other.

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects

“…So the bulk current injected from the junctions can further be neglected. On the other hand coupling from the noisy power supply via substrate contacts remains the dominant mechanism, as previously demonstrated by measurements [10].…”

“…The contribution of the substrate, which can be modeled by a resistive network extracted with SubstrateStorm [11], to the overall Y 11 (jω) is negligible for high-ohmic substrates [10] (see Fig. 1 for a 2-input NAND gate) for any digital gate.…”

“…As shown in [10] the circuit admittance (mainly a capacitance) is logic-state dependent. For a single gate the variation can be up to 6 %.…”

Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance

“…Note that is the summation of the intentional decoupling capacitance and the intrinsic capacitance of the nonswitching gates within a circuit [21]. Techniques to estimate this capacitance are described in [22]. The load circuit is represented by a current source with a transition time and peak current .…”

“…Note that the intrinsic capacitance between the power and ground networks due to the nonswitching gates contributes to the overall decoupling capacitance. For sufficiently large circuits, this capacitance can be significant [21], [22], that is, the assumption of fast current transients as the worst case scenario is overly optimistic for large-scale circuits.…”