Digital column readout architecture for the ATLAS pixel 0.25 /spl mu/m front end IC

Mandelli, E.; Blanquart, L.; Denes, P.; Einsweiler, K.; Marchesini, Roberto; Meddeler, G.; Ackers, M.; Fischer, P.; Comes, G.; Perić, I.

doi:10.1109/tns.2002.801528

Cited by 16 publications

(13 citation statements)

References 6 publications

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“…The area of the pixel modules will be increased and the instantaneous luminosity is expected to reach values about ten times its current nominal value. For the ATLAS ITk, from its outer to innermost layers, these conditions will translate into a particle occupancy from 1 to 30 MHz/mm 2 , non-ionising displacement damage (NIEL) between 10 15 and 10 16 n eq /cm 2 and doses from ionizing radiation (TID) between 80 and 10 3 Mrad by the end of its lifetime.…”

mentioning

confidence: 99%

The Monopix chips: depleted monolithic active pixel sensors with a column-drain read-out architecture for the ATLAS Inner Tracker upgrade

Caicedo¹,

Barbero²,

Barrillon³

et al. 2019

J. Inst.

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A: Two different depleted monolithic CMOS active pixel sensor (DMAPS) prototypes with a fully synchronous column-drain read-out architecture were designed and tested: LF-Monopix and TJ-Monopix. These chips are part of a R&D effort towards a suitable implementation of a CMOS DMAPS for the HL-LHC ATLAS Inner Tracker. LF-Monopix was developed using a 150nm CMOS process on a highly resistive substrate (>2 kΩ cm), while TJ-Monopix was fabricated using a modified 180 nm CMOS process with a 1 kΩ cm epi-layer for depletion. The chips differ in their front-end design, biasing scheme, pixel pitch, dimensions of the collecting electrode relative to the pixel size (large and small electrode design, respectively) and the placement of read-out electronics within such electrode.Both chips were operational after thinning down to 100 µm and additional back-side processing in LF-Monopix for total bulk depletion. The results in this work include measurements of their leakage current, noise, threshold dispersion, response to minimum ionizing particles and efficiency in test beam campaigns. In addition, the outcome from measurements after irradiation with neutrons up to a dose of 1 × 10 15 n eq /cm 2 and its implications for future designs are discussed.

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mentioning

confidence: 99%

The Monopix chips: depleted monolithic active pixel sensors with a column-drain read-out architecture for the ATLAS Inner Tracker upgrade

Caicedo¹,

Barbero²,

Barrillon³

et al. 2019

J. Inst.

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“…Inheriting from the LF-CPIX design, the LF-Monopix1 chip has greatly enhanced the capability of pixel-level digital processing [10,26]. It incorporates the so called column drain readout architecture, which was established for hybrid pixel readout chips and has been used by the current ATLAS pixel detector [27][28][29]. The expected rate capability for a full scale sensor chip (i.e.…”

Section: Lf-monopix1mentioning

confidence: 99%

Radiation hard DMAPS pixel sensors in 150 nm CMOS technology for operation at LHC

Barbero¹,

Barrillon²,

Bespin³

et al. 2020

J. Inst.

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“…In addition, in these experiments innermost detectors are generally composed of solid-state devices such as arrays of silicon pixels. The choice relies on the small pixel dimension that allows for a very high spatial resolution, of the order of tens of μ m [ 30 – 32 ]. These inner detectors, basically, just detect the passage, or not passage, of ionizing particles through the matter and, for this reason, these apparatus are called trackers [ 33 , 34 ].…”

Section: Electronics For Particle Collidersmentioning

confidence: 99%

“…For this reason in many HEPE some registers are inserted within the pixels; however, here it has been chosen to design a very simple pixel and move the readout electronics outside the matrix of sensors. This is deemed particularly useful for small (of the order of 100 μ m 2 ) active pixel sensors such as those exploited for future colliders [ 32 – 34 , 38 , 39 ]. This also allows for designing and exploiting larger matrices of pixels.…”

Section: Electronics For Particle Collidersmentioning

confidence: 99%

Fast Readout Architectures for Large Arrays of Digital Pixels: Examples and Applications

Gabrielli

2014

The Scientific World Journal

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Modern pixel detectors, particularly those designed and constructed for applications and experiments for high-energy physics, are commonly built implementing general readout architectures, not specifically optimized in terms of speed. High-energy physics experiments use bidimensional matrices of sensitive elements located on a silicon die. Sensors are read out via other integrated circuits bump bonded over the sensor dies. The speed of the readout electronics can significantly increase the overall performance of the system, and so here novel forms of readout architectures are studied and described. These circuits have been investigated in terms of speed and are particularly suited for large monolithic, low-pitch pixel detectors. The idea is to have a small simple structure that may be expanded to fit large matrices without affecting the layout complexity of the chip, while maintaining a reasonably high readout speed. The solutions might be applied to devices for applications not only in physics but also to general-purpose pixel detectors whenever online fast data sparsification is required. The paper presents also simulations on the efficiencies of the systems as proof of concept for the proposed ideas.

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Digital column readout architecture for the ATLAS pixel 0.25 /spl mu/m front end IC

Cited by 16 publications

References 6 publications

The Monopix chips: depleted monolithic active pixel sensors with a column-drain read-out architecture for the ATLAS Inner Tracker upgrade

The Monopix chips: depleted monolithic active pixel sensors with a column-drain read-out architecture for the ATLAS Inner Tracker upgrade

Radiation hard DMAPS pixel sensors in 150 nm CMOS technology for operation at LHC

Fast Readout Architectures for Large Arrays of Digital Pixels: Examples and Applications

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