Digital implementation of biologically inspired Wilson model, population behavior, and learning

This paper presents an optimized stochastic multiplier to implement Izhikevich spiking neuron model. A novel stochastic number generator is used as the main block for stochastic computing to design a stochastic multiplier. The designed multiplier was used to describe and implement Izhikevich neuron model equation which is capable to produce variant responses of spiking neurons. To the best of the author's knowledge, this work is the pioneer using a designed multiplier for computing all of the multiplication expressions in spiking neuron equation. The effect of increasing number of bit streams on the accuracy of stochastic computing is studied. Furthermore, some numerical intervals that are more prone to the error are found and illustrated upon stochastic computing usage, and a method is proposed to improve the error prone numerical intervals. In addition, the response accuracy is optimized by changing time step parameter in solving ordinary differential Izhikevich neuron model equation using Euler's method. Hence, a 13‐bit stochastic multiplier is designed. It is found that variations in parameters a and b have a profound effect on the accuracy of recovery variable u and, consequently, on the responses. Out of 20 responses of Izhikevich neuron model, 11 responses are generated using the proposed stochastic computing method and compared with piecewise linear method and some previous architectures of Izhikevich neuron model implementations.

Section: Introductionmentioning

confidence: 99%

Implementation of Izhikevich neuron based on stochastic computing using a novel inspired Omega‐Flip stochastic number generator

Hedayatpour

Karami

Shamsi

2022

“…Moreover, the logic capacity of FPGA to implement complex neural algorithms and prototypes without requiring VLSI chip fabrication makes it a brilliant choice. [19][20][21][22][23][24][25][26][27][28][29][30][31] FPGA-based on-chip learning and off-chip learning, which are sometimes known as online learning and offline learning, are the main methods for learning implementation in the hardware at register transfer level (RTL). 26,27 Motivated by these findings, this paper proposes an efficient and high-speed reconfigurable digital implementation of an SNN using Izhikevich neurons and gradient descent learning on an FPGA to approximate the sigmoid function.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable field‐programmable gate array‐based on‐chip learning neuromorphic digital implementation for nonlinear function approximation

Gholami

Farsa

Karimi

2021

Self Cite

Hardware implementations of spiking neural networks, which are known as neuromorphic architectures, provide an explicit understanding of brain performance. As a result, biological features of the brain may well inspire the next generation of computers and electronic systems used in such areas as signal processing, image processing, function approximation, and pattern recognition. Approximating nonlinear functions has many uses in computer science and applied mathematics. The sigmoid is the most universal activation function in neural networks by which the relationship between biological and artificial neurons is defined. It is a suitable option for predicting the probability of anything from 0 to 1 as output. In this paper, a spiking neural network using Izhikevich neurons and a gradient descent learning algorithm are propounded to approximate the sigmoid and other nonlinear functions. The flexibility of the spiking network is demonstrated by showing the average relative errors in the approximation process. A time-and cost-efficient digital neuromorphic implementation on the base of on-chip learning method for approximating the sigmoid function is also discussed. The paper reports the results of the hardware synthesis and the spiking network's physical implementation on a field-programmable gate array. The maximum frequency and throughput of the implemented network were 83.209 MHz and 9.86 Mb/s, respectively. K E Y W O R D Sdigital hardware, field-programmable gate array (FPGA), hardware implementation, neuromorphic, on-chip learning, spiking neural networks (SNNs)

“…19,20 The FPGA-based method exploits lower development time, lower cost, reconfigurability, and concurrent computing which has attracted a considerable attention to digital SNN accelerators. [21][22][23] Previously, numerous FPGA-based designs of SNN with different architectures have been investigated for various applications. Previous works, from single neurons to an extensive biologically plausible network, have implemented on the FPGA.…”

Section: Introductionmentioning

confidence: 99%

A reconfigurable real‐time neuromorphic hardware for spiking winner‐take‐all network

Abdoli

Safari

2020

The central nervous system receives a vast amount of sensory inputs, and it should be able to discriminate and recognize different kinds of multisensory information. Winner-take-all (WTA) consists of a simple recurrent neural network carrying out discrimination of input signals through competition. This paper presents a real-time scalable digital hardware implementation of the spiking WTA network. The need for concurrent computing, real-time performance, proper accuracy, and the reconfigurable device has led to the fieldprogrammable gate array (FPGA) as the target hardware platform. A set of techniques is employed to lessen memory and resource usage. The proposed architecture consists of multiprocessing elements, which share hardware resources between a specific number of neurons. We introduce a novel connectivity array for neurons (dedicated to the WTA network) to cut down memory usage. Also, a multiplier-less method in the neuron model and a novel tree adder in the synapse processing unit are designed to improve computational efficiency. The proposed network simulates 4,500 neurons in real time on a Xilinx Artix-7 FPGA, while a scalable architecture facilitates the implementation of up to 20,000 neurons on this device. The pipeline structure can guarantee real-time performance for large-scale networks. Based on simulation and physical synthesis results, the presented network mimics biological WTA dynamics and consumes efficient hardware resources.