Digital implementation of cellular sensor‐computers

Abstract

correspondence between the sensors and the processors, and the sensor and processor arrays are mapped into each other. Since the processors in these implementations occupy significant silicon area, the pitch size of these sensor-processor chips is between 50-200 microns. This yields a low fill-factor (5-15%); moreover, it prevents building high resolution (like 1024x1024) arrays. The largest operational combined sensor-processor array is the ACE16k [8]. It was implemented on 0.35 micron technology, and its size is 128x128. However, this focal-plane sensor-processor array can easily capture and process up to 50,000 FPS real-time, which makes them the fastest image processor devices in the world; it is not usable in many applications, where higher resolution is required. A new version of the ACE16k, currently under development, will step down to 0.18 micron, and reach roughly 20-micron pitch size and QZIF resolution.Some applications, like surface inspection, image enhancement requires the analysis of the entire image continuously, hence the one-to-one correspondence of the sensors and the processors is needed. In the first part of this paper, we are going to introduce the digital implementation of the cellular sensor-computer architecture. In the third chapter, we describe the instruction set and computational performance. Later on, considerations of the technology scaling down and its effect on the implementation are given. Later on, implementation studies are presented and finally we conclude our work. II. SYSTEM ARCHITECTURE OVERVIEWThe system architecture of the cellular sensor computer is introduced here has been developed to integrate the essential tasks in the same entity, namely the sensing, the tightly coupled parallel processing, and a top level communication and algorithmic control. The name of the game in all focal plane array processor implementation is the spatial resolution. The higher the spatial resolution (pixel count) the more precise image sensing and processing operations can be achieved. This certainly means that we have to minimize all the circuits, to be able to shrink the pitch size as much as possible.In the digital domain, the simplest processor techniques are the bit sliced architectures. Though these processors can deal with a single bit in a clock cycle, in a sequence of clock cycles, it can calculate with arbitrary precision numbers. In image processing applications, 4-16 bits precision is typically enough. The advantage of the architecture is that the execution time is proportional with the precision, which makes possible finding trade-offs between precision and execution time.From implementation point of view, the integration of the different functionalities, like sensing, processing, and control, means a solution for different preferences. These preferences can be high speed sensing, less design effort, or high spatial resolution. The different aims directs to different implementation of the same system idea. Our answers for the above three preferences are the integrated sensor-p...

Configurable 3D‐integrated focal‐plane cellular sensor–processor array architecture

“…In the design of focal-plane sensor-processor arrays, there are several tight trade-offs [1,[15][16][17][18]. One of them is the antagonism of the required sensor resolution and the attached processing power.…”

“…The high-level organization of the integrated sensor interface processor array [1,23] is shown in Figure 2. As it can be seen from the figure, each array is embedded into a relatively simple shell.…”

“…The architecture is derived from the concept introduced in [1]. Its functionality, near-sensorprocessing capability, and topographic architecture are inspired by the Cellular Neural Network Universal Machines [2][3][4][5].…”

Stochastic bitstream‐based CNN and its implementation on FPGA

“…In the past 15 years, since the invention of cellular nonlinear network (CNN) [1,2], many algorithms have been published and several hardware realizations have been introduced on the market [3][4][5][6][7]. After the first successfully functioning analog CNN chips (Ace4k, Ace16k and CACE1, sized 64×64, 128×128 and 32×32 [8][9][10]) and systems (e.g.…”

“…Bi-i and for SCAMP3 [11,12]) using these chips, the development and implementation of new chips and systems are in progress and can be reached on the market (EyeRis I and II [4]). Besides, the analog implementations attempts have been made to design fully digital versions [6,[13][14][15]. The comparison of the various CNN implementations can be found in [13], which also presents an emulated digital cellular nonlinear…”