Digital Implementation of Pulse Compression Technique for X-band Radar

This paper presents an ultra-high-speed correlation processor for FPGA (Field-Programmable Gate Array) which is based on MDF (multiplepath delay feedback) pipelined FFT (fast Fourier transform) architecture. In order to decrease the resource cost and processing delay, the FFT processor is based on DIF (Decimation in Frequency) decomposition method, and the IFFT processor is based on DIT (Decimation in Time) decomposition method. The data input and output of the correlation processor are both in natural order. The main clock speed of the processor FPGA implementation can be higher than 200 MHz and is able to process continuous complex input at more than 1.6 Gsps (giga samples per second).

Section: Fpga Design (1) Data Memorymentioning

confidence: 99%

“…Next a N 1 point FFT is computed. In equation (6), first the internal N 1 point IFFT is computed. Then, it is multiplied by the phase factor W Àn 1 k 2 N .…”

Section: Mdf Fft/ifft Processor Algorithm Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An ultra-high-speed FPGA based digital correlation processor

Altaf

Ahmad

Wei³

et al. 2015

“…With the development of digital processing devices, it is more appreciated to implement the pulse compression using digital devices. The most popular approach is FFT + Multiply + IFFT, which takes advantage of the fact that convolution in the time domain is equivalent to multiplication in the frequency domain [1,2,3,4,5,6,7,8].…”

Section: Introductionmentioning

confidence: 99%

Design and FPGA implementation of digital pulse compression for chirp radar based on CORDIC

Yan

Wen

Wang

et al. 2009

“…For chirp (linear FM, LFM) radar, there are many pulse compression methods, in which the most popular techniques are matched filtering and de-chirp demodulation combined with Fast Fourier transform (FFT) techniques [1,2,3,4,5,6]. The matched filter may be implemented by using a digital convolution in time-domain or frequency-domain [1], but the main drawback of matched filtering is the complexity for hardware implementations when the time-bandwidth product of the chirp signal is large [7].…”

Section: Introductionmentioning

confidence: 99%

Design and FPGA implementation of digital pulse compression for HF chirp radar based on modified orthogonal transformation

Wang

Gao

Zhou

et al. 2011

Abstract:The paper presents a digital pulse compression approach for high frequency (HF) chirp radar. The emphasis is to accomplish echo signal de-chirp operation by modified orthogonal transformation on field programmable gates array (FPGA) chip. This approach has been developed for an all-digital receiver platform which is directly radio frequency (RF) band-pass sampling, compared with the traditional analog receiver or intermediate frequency (IF) receiver, it has an easy hardware structure closing to a "soft" radar mode. The system closedloop test shows the correctness and rationality of the design, meeting the demand of engineering application.