Digital Multiplierless Realization of a Calcium-Based Plasticity Model

Jokar, Ehsan; Soleimani, Hamid

doi:10.1109/tcsii.2016.2621823

Cited by 24 publications

(17 citation statements)

References 7 publications

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“…There are some more recent works reporting on STDP based synapses implemented on FPGAs (Pedroni et al, 2016 ; Jokar and Soleimani, 2017 ; Nouri et al, 2018 ; Lammie et al, 2018 ). Unfortunately, hardware resources are reported only for a single STDP synapse/unit, making it difficult to compare with a full STDP system implementation, since it is not clear how reported synaptic resources can be shared or time-multiplexed at system level.…”

Section: Discussionmentioning

confidence: 99%

On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights

et al. 2018

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In computational neuroscience, synaptic plasticity learning rules are typically studied using the full 64-bit floating point precision computers provide. However, for dedicated hardware implementations, the precision used not only penalizes directly the required memory resources, but also the computing, communication, and energy resources. When it comes to hardware engineering, a key question is always to find the minimum number of necessary bits to keep the neurocomputational system working satisfactorily. Here we present some techniques and results obtained when limiting synaptic weights to 1-bit precision, applied to a Spike-Timing-Dependent-Plasticity (STDP) learning rule in Spiking Neural Networks (SNN). We first illustrate the 1-bit synapses STDP operation by replicating a classical biological experiment on visual orientation tuning, using a simple four neuron setup. After this, we apply 1-bit STDP learning to the hidden feature extraction layer of a 2-layer system, where for the second (and output) layer we use already reported SNN classifiers. The systems are tested on two spiking datasets: a Dynamic Vision Sensor (DVS) recorded poker card symbols dataset and a Poisson-distributed spike representation MNIST dataset version. Tests are performed using the in-house MegaSim event-driven behavioral simulator and by implementing the systems on FPGA (Field Programmable Gate Array) hardware.

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Section: Discussionmentioning

confidence: 99%

On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights

et al. 2018

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“…12,13 Today, research on designing neuromorphic systems for those applications that require precise calculations and high precision of neuronal parameters has a high priority in the field. 3,[14][15][16][17][18][19][20][21][22] Networks with reduced precision of weights show severely reduced performance in many applications. For instance, only 68% accuracy on the ImageNet dataset after optimization for an 8-bit precision network was reported in Rusci et al 23 Moreover, networks with course discretization of weights are more prone to adversarial attacks.…”

Section: Introductionmentioning

confidence: 99%

“…[29][30][31] Several attempts have been made to develop synaptic plasticity in very large scale integration (VLSI) technologies, 31,32 eg, analog plastic synapses, 33,34 mixed-signal learning rules, 35 memristor-based adaptation algorithms, 36,37 and digital models. 18,[38][39][40] While analog (mixed-signal) VLSI and memristor-based devices often require less area and show lower power consumption, they are not easily reconfigurable for studying different algorithms. Reconfigurability and flexibility of FPGAs, to the contrary, make them a better suitable substrate for studying different neurally based models.…”

Section: Introductionmentioning

confidence: 99%

“…Reconfigurability and flexibility of FPGAs, to the contrary, make them a better suitable substrate for studying different neurally based models. 14,18,41,42 In digital neural models, efficient methods for implementing bio-inspired circuits have been developed. Several researchers suggested piece-wise linear approximations, memory look-up tables, and shift-add multiplication techniques for reducing implementation complexities of neuromorphic designs.…”

Section: Introductionmentioning

confidence: 99%

“…Several researchers suggested piece-wise linear approximations, memory look-up tables, and shift-add multiplication techniques for reducing implementation complexities of neuromorphic designs. [14][15][16][17][18][19][20]43 Following these research lines, in this study, we present digital multiplier-less neuromorphic realizations of two types of the long-term plastic synapses. In one of them, the synaptic efficacy alters based on the post-synaptic depolarization and the calcium concentration in the post-synaptic neuron on the arrival of a pre-synaptic spike (SSSTDP model).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Digital multiplier‐less implementation of high‐precision SDSP and synaptic strength‐based STDP

Asgari

Maybodi

Sandamirskaya

2020

Circuit Theory & Apps

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Spiking neural networks (SNNs) can achieve lower latency and higher efficiency compared with traditional neural networks if they are implemented in dedicated neuromorphic hardware. In both biological and artificial spiking neuronal systems, synaptic modifications are the main mechanism for learning. Plastic synapses are thus the core component of neuromorphic hardware with on-chip learning capability. Recently, several research groups have designed hardware architectures for modeling plasticity in SNNs for various applications. Following these research efforts, this paper proposes multiplier-less digital neuromorphic circuits for two plasticity learning rules: the spike-driven synaptic plasticity (SDSP) and synaptic strength-based spike timing-dependent plasticity (SSSTDP). The proposed architectures have increased the precision of the plastic synaptic weights and are suitable for spiking neural network architectures with more precise calculations. The proposed models are validated in MATLAB simulations and physical implementations on a field-programmable gate array (FPGA). KEYWORDSFPGA, neuromorphic engineering, plastic synapse, spiking neural network (SNN) Int J Circ Theor Appl. 2020;48:724-738. wileyonlinelibrary.com/journal/cta

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Multiplierless low‐cost implementation of Hindmarsh–Rose neuron model in case of large‐scale realization

Haghiri

Yahya

Rezaei

et al. 2023

Circuit Theory & Apps

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Implementation of neural networks in case of hardware helps us to understand the different parts of the human brain operation, using artificial intelligence (AI). This paper presents a new model of the Hindmarsh-Rose (HR) Neuron that is based on basic polynomial functions called Nyquist-look up table-Hindmarsh-Rose (N-LUT-HR) based on an accurate sampling of the original model. The proposed approach is investigated in terms of its digital realization feasibility. According to high matching between the original and proposed terms, it is showed that the new modified model can follow all spiking patterns of primary model with low-error computations. In hardware case, the proposed and original models are implemented on Xilinx FPGA XC2VP30 chip to validate different aspects of the simulation results. Hardware results demonstrate that our model regenerates the desired patterns in low-cost and high-frequency (speed-up) in comparison with the other similar works. Overall saving in FPGA resources show that this new model is capable of being used in large-scale networks in case of minimum required resources (FPGA costs). In addition, the analysis of hardware indicates that the new circuits can work in a maximum frequency of 123 MHz with 98.25% saving in FPGA costs (resources utilization of FPGA).

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Digital Multiplierless Realization of a Calcium-Based Plasticity Model

Cited by 24 publications

References 7 publications

On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights

On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights

Digital multiplier‐less implementation of high‐precision SDSP and synaptic strength‐based STDP

Multiplierless low‐cost implementation of Hindmarsh–Rose neuron model in case of large‐scale realization

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