Digital neural network implementation

Swartzlander, Earl E.; Jones, R. Forbes

doi:10.1109/pccc.1992.200512

Cited by 13 publications

(3 citation statements)

References 6 publications

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“…Parallel counters are multi-input, multi-output combinational logic circuits that determine the number of logic ONE's in their input vectors and generate a binary coded output vector which corresponds to this number [1,2]. A wide variety of parallel counter architectures that exist in literature [4][5][6] have been summarized in [3].…”

Section: Introductionmentioning

confidence: 99%

Novel architectures for efficient (m, n) parallel counters

Veeramachaneni

Lingamneni

Krishna

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3), (15, 4) and (31,5) counters capable of operating at ultra-low voltages are presented. Based on these counters, a generalized architecture is derived for large (m, n) parallel counters. The proposed architecture lays emphasis on the use of multiplexers and a combination of CMOS and transmission gate logic in arithmetic circuits that result in high speed and efficient design. The proposed counter designs have been compared with existing designs and are shown to achieve an improvement of about 45% in delay and a reduction of about 25% in power consumption.

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Section: Introductionmentioning

confidence: 99%

Novel architectures for efficient (m, n) parallel counters

Veeramachaneni

Lingamneni

Krishna

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

show abstract

“…Parallel counters are useful in implementing fast multipliers [1], [2], multioperand adders [3], [4], and digital neural networks [5]. Previous counter designs include: quasi-digital [6], threshold gate [1], residue threshold function [3], thermometer code [4], and switching tree logic [7] implementations.…”

Section: Introductionmentioning

confidence: 99%

“…Design trade-offs are examined regarding the use of counter cells [5], [6], [8], of size ranging from (3,2) to (31,5) as building blocks. The design of the counter blocks will be examined first, followed by four example large counter designs.…”

Section: Introductionmentioning

confidence: 99%