Direct and indirect causes of Fermi level pinning at the SiO∕GaAs interface

Winn, Darby L.; Hale, Michael; Grassman, Tyler J.; Kummel, Andrew C.; Droopad, R.; Passlack, M.

doi:10.1063/1.2363183

Cited by 30 publications

(27 citation statements)

References 54 publications

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“…This finding agrees with that of Winn's work. 9 For the F and Cl cases, F and Cl obtain 0.61 and 0.46 electrons from the adjacent undimerized As atom, respectively. Therefore, F and Cl help to compress the gap bands induced by specific As dangling bonds into the conducting region.…”

Section: Electronic Structures Of Passivation Of Oxidized Gaas"001…-␤mentioning

confidence: 99%

“…6 The oxidation and passivation of a GaAs͑001͒ surface are important issues of GaAs-based MOSFETS, thus of great interest to researchers. Previous work [7][8][9] studied diverse surface oxidation models, including SiO adsorption and the replacement of As dimer atoms by two oxygen atoms on GaAs͑001͒ surface. Their results showed that a possible mechanism of Fermi level pinning is not due to the intrinsic properties of GaAs͑001͒ surface, but due to the specific bonding geometries resulting from the oxidation.…”

Section: Introductionmentioning

confidence: 99%

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First-principles study of GaAs(001)-β2(2×4) surface oxidation and passivation with H, Cl, S, F, and GaO

Wang

Lee

Huang

et al. 2010

Journal of Applied Physics

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The interactions of oxygen atoms on the GaAs(001)-β2(2×4) surface and the passivation of oxidized GaAs(001)-β2(2×4) surface were studied by density functional theory. The results indicate that oxygen atoms adsorbed at back-bond sites satisfy the bond saturation conditions and do not induce surface gap states. However, due to the oxygen replacement of an As dimer atom at a trough site or row site, the As–As bond is broken, and gap states are produced leading to the Fermi level pinning because of unsaturated As dangling bonds. Atomic H, Cl, S, F, and the molecular species GaO were examined to passivate the unsaturated As dangling bond. The results show that H, Cl, F, and GaO can remove such gap states. It is also found that the interaction of S with the unsaturated As dangling bond does not remove the gap states, and new gap states are generated upon single S adsorption. A higher S coverage forms S–S dimer pairs which passivate two unsaturated As atoms, and removes the As-induced gap states.

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Section: Electronic Structures Of Passivation Of Oxidized Gaas"001…-␤mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

First-principles study of GaAs(001)-β2(2×4) surface oxidation and passivation with H, Cl, S, F, and GaO

Wang

Lee

Huang

et al. 2010

Journal of Applied Physics

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“…This SiO x layer could be a direct cause of Fermi-level pinning, as reported recently. 16 The capacitance-voltage ͑C-V͒ characteristics of samples with Al 2 O 3 deposited directly on the NH 4 OH and hydrogentreated n-type GaAs ͑100͒ surfaces show the same amount of accumulation capacitance ͑C acc ͒ frequency dispersion for both types of surface preparations ͑not shown͒. These similarities, despite the different starting surfaces, are probably due to the comparable number of interfacial oxide bonds after dielectric deposition due to the subsequent exposure to oxygen from H 2 O in the ALD cycles.…”

mentioning

confidence: 99%

Frequency dispersion reduction and bond conversion on n-type GaAs by in situ surface oxide removal and passivation

Hinkle

Sonnet

Vogel

et al. 2007

Applied Physics Letters

101

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The method of surface preparation on n-type GaAs, even with the presence of an amorphous-Si interfacial passivation layer, is shown to be a critical step in the removal of accumulation capacitance frequency dispersion. In situ deposition and analysis techniques were used to study different surface preparations, including NH 4 OH, Si-flux, and atomic hydrogen exposures, as well as Si passivation depositions prior to in situ atomic layer deposition of Al 2 O 3 . As-O bonding was removed and a bond conversion process with Si deposition is observed. The accumulation capacitance frequency dispersion was removed only when a Si interlayer and a specific surface clean were combined. © 2007 American Institute of Physics. ͓DOI: 10.1063/1.2801512͔GaAs has once again attracted attention as an alternative substrate for metal oxide semiconductor ͑MOS͒ technologies. The advantages of GaAs over silicon are well-known, mainly having a higher electron mobility and breakdown voltage as well as a direct band gap suggesting GaAs for a wide range of devices. The elimination of anomalous frequency dispersion of the accumulation capacitance of GaAs MOS devices is a major motivation behind surface and interface treatment studies. Previous reports have attributed this dispersion, viz., the reduction of maximum capacitance with increasing measurement frequency, to a high density of interface states which results in Fermi-level pinning. Recent studies have indicated that the disruption of As-O bonding at the dielectric/GaAs interface results in an unpinned interface. 1 Revisiting earlier works on Si passivation of GaAs surfaces ͑see, for example, Refs. 2 and 3͒, recent reports of Si deposition on GaAs for surface passivation in conjunction with high-k dielectrics ͑for example, Refs. 4 and 5͒, have stimulated this study using in situ deposition and analysis methods. In this letter, in situ analysis techniques are used to correlate differences in electrical characteristics caused by different surface treatments employed on the technologically relevant n-type GaAs surface for use in enhancement mode transistors.The samples used in this work were n-type Si-doped GaAs wafers with a doping concentration of 5 ϫ 10 17 cm −3 . One set of samples was degreased in acetone, methanol, and isopropyl alcohol for 1 min each, followed by a 3 min etch in 29% NH 4 OH, 6 and dried with N 2 , while another set was prepared, in situ with no chemical treatment, using a hydrogen cracker source ͑cell temperature of 1400°C, P H 2 =1 ϫ 10 −6 mbar͒ producing atomic H with a substrate temperature of 430°C for 30 min. 7,8 Silicon of various thicknesses was deposited at room temperature on treated GaAs by e-beam evaporation ͑deposition rate= 18-132 Å / min in a multitechnique deposition/characterization system ͑base pressure= 2 ϫ 10 −11 mbar͒. 9 MOS capacitors were made using such treated surfaces followed by atomic layer deposition ͑ALD͒ of 10 nm of Al 2 O 3 using trimethylaluminum ͑TMA͒ and H 2 O at 300°C in an adjacent chamber and ex situ, rf sputtered TaN as the gat...

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“…Previous work [25][26][27] studied diverse surface oxidation models, and their results showed that a possible mechanism of Fermi-level pinning is not due to the intrinsic properties of GaAs (001) surface, but due to the specific bonding geometries resulting from the oxidation. Recently, based on scanning tunneling [17].)…”

Section: Gaas Surface Oxidationmentioning

confidence: 99%

“…Recently, based on scanning tunneling [17].) spectroscopy (STS) and DFT studies for different adsorbates on the GaAs (001) surface, Winn et al [27] have proposed that the Fermi-level pinning mechanisms could be either direct or indirect. The direct Fermi-level pinning is due to the gap states induced by the adsorbate, while the indirect Fermi-level pinning is due to the gap states induced by the secondary effects, such as the generation of undimerized As atoms.…”

Section: Gaas Surface Oxidationmentioning

confidence: 99%

Theoretical Progress on GaAs (001) Surface and GaAs/High‐ k Interface

Wang

Xiong

Wallace

et al. 2012

High‐k Gate Dielectrics for CMOS Technology

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The recent resurgence of interest in III-V transistor channel materials has come about due to the scaling requirement of Si-based metal oxide semiconductor (MOS) devices [1]. III-V channel materials have much higher bulk electron mobilities than Si (see Table 13.1) and thus expected to provide high channel injection velocities. Among the III-V compounds, gallium arsenide (GaAs) is a prototype material because of its many advantages, such as, 5Â higher electron mobility than Si, the availability of semiinsulating GaAs substrates, and a higher breakdown field over Si to achieve GaAs-based high-speed devices.Nevertheless, III-V materials suffer from a lack of thermodynamically stable gate dielectrics [2], with an acceptable low density of III-V/dielectric interface states, which makes it very difficult to be implemented into future CMOS-type devices. The interfacial density of states (D it ) leads to many problems such as Fermi-level pinning, reduced electron mobility, and instability of device operations. The Fermi-level pinning results in the loss of the modulation of the carrier concentration at the oxide/III-V interface by the gate bias. For oxide/III-V interfaces, the interfacial group III-or V-dangling bonds are partially saturated [3] and they can hardly be fully saturated to obtain a superior high-k/III-V interface with low D it . Furthermore, the partially saturated bonds can induce mid-gap states that lead to Fermi-level pinning. This pinning is most likely due to the presence of III(V)-O bonds and the resultant structural disorders. Therefore, understanding the oxidation and passivation mechanisms of the III-V surface are very useful to gain an important insight to control the quality of high-k/III-V interfaces [4][5][6][7][8].When high-k oxides are deposited upon III-V materials, the III-V/high-k oxide interfaces are much more complicated than the ideal III-V surface alone. The low electronic quality of an III-V/dielectric interface can be attributed to several reasons.High-k Gate Dielectrics for CMOS Technology, First Edition. Edited by Gang He and Zhaoqi Sun.

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Direct and indirect causes of Fermi level pinning at the SiO∕GaAs interface

Cited by 30 publications

References 54 publications

First-principles study of GaAs(001)-β2(2×4) surface oxidation and passivation with H, Cl, S, F, and GaO

First-principles study of GaAs(001)-β2(2×4) surface oxidation and passivation with H, Cl, S, F, and GaO

Frequency dispersion reduction and bond conversion on n-type GaAs by in situ surface oxide removal and passivation

Theoretical Progress on GaAs (001) Surface and GaAs/High‐ k Interface

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