Direct liquid cooling of a stacked multichip module

Chen, X.Y.; Toh, K.C.; Chai, John C.; Pinjala, D.

doi:10.1109/eptc.2002.1185702

Cited by 16 publications

(6 citation statements)

References 21 publications

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“…Other concepts use [1-mm-thick interlayer heat spreaders to conduct the heat laterally out of the stack (Lee et al 2005). Also convective interlayer heat removal was investigated by several researchers (Takahashi et al 2004;Chen et al 2002;Koo et al 2005). Takahashi and Chen demonstrated removal of 25 W/cm 2 with water as coolant and a die spacing of 10 lm for die stacks with peripheral interconnects and a 10-mm parallel-plate heat-transfer configuration.…”

Section: Introductionmentioning

confidence: 99%

Interlayer cooling potential in vertically integrated packages

et al. 2008

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The heat-removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters <= 200 mu m. An experimental investigation with uniform and double-side heat flux at Reynolds numbers <= 1,000 and heat transfer areas of 1 cm(2) was carried out to identify the most efficient interlayer heat-removal structure. The following structures were tested: parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 mu m and fluid structure heights of 100-200 mu m. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin in-line structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks having a 4-cm(2) heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from > 200 W/cm(2) at 1 cm(2) and > 50 mu m interconnect pitch to < 100 W/cm(2) at 4 cm(2). From experimental data, friction factor and Nusselt number correlations were derived for pin fin in-line and staggered structures

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Section: Introductionmentioning

confidence: 99%

Interlayer cooling potential in vertically integrated packages

et al. 2008

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“…Many researchers have explored the advantages of using liquid cooling to tackle high heat flux problem [4][5][6]. But many challenges have not been addressed for the integration of liquid cooling in 3-D package such as embedding microchannels in the chip carrier, 3-D fluidic interconnection and fluidic sealing.…”

Section: Introductionmentioning

confidence: 99%

3D packaging with through ilicon via (TSV) for electrical and fluidic interconnections

Khan

et al. 2009

2009 59th Electronic Components and Technology Conference

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In this paper a liquid cooling solution has been reported for 3-D package in PoP format. The high heat dissipating chip is mounted on a silicon carrier, which has copper through-silicon via for electrical interconnection and throughsilicon hollow via for fluidic circulation. Heat enhancement structures have been embedded in the chip carrier. Cooling liquid, de-ionized water is circulated through the chip carrier and heat from the chip is extracted. The fluidic channels are isolated from electrical traces using hermetic sealing. The research work has demonstrated 100 W of heat dissipation from one stack and total of 200 W from two stacks of the package. The fluidic interconnections and sealing techniques have been discussed.

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“…If the 3D integration technique is applied in designing multi-core processors with conventional air cooling, the thermal problems are expected to be more serious, since the power density increases and heat dissipation distance becomes longer as multiple dies are stacked vertically. To mitigate thermal problems in 3D processors with more aggressive cooling methods, the interlayer liquid cooling methods using water as a coolant have been investigated by several researchers [6,8,22]. Especially, Brunschwiler et al examined the heat dissipation capability of direct liquid cooling at practical operation conditions based on the most recent liquid cooling scheme proposed by IBM Corporation [6].…”

Section: Introductionmentioning

confidence: 99%

Quantifying Architectural Impact of Liquid Cooling for 3D Multi-Core Processors

Jang¹,

Yoon²,

Kim³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-For future multi-core processors, 3D integration is regarded as one of the most promising techniques since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Conventional air cooling schemes are not enough for 3D multi-core processors due to the limit of the heat dissipation capability. Without more efficient cooling methods such as liquid cooling, the performance of 3D multi-core processors should be degraded by dynamic thermal management. In this paper, we examine the architectural impact of cooling methods on the 3D multi-core processor to find potential benefits of liquid cooling. We first investigate the thermal behavior and compare the performance of two different cooling schemes. We also evaluate the leakage power consumption and lifetime reliability depending on the temperature in the 3D multi-core processor.

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Direct liquid cooling of a stacked multichip module

Cited by 16 publications

References 21 publications

Interlayer cooling potential in vertically integrated packages

Interlayer cooling potential in vertically integrated packages

3D packaging with through ilicon via (TSV) for electrical and fluidic interconnections

Quantifying Architectural Impact of Liquid Cooling for 3D Multi-Core Processors

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