Direct tunneling RAM (DT-RAM) for high-density memory applications

Abstract

A new approach to reducing the tunnel oxide thickness in floating gate memories is introduced for RAM applications. Experimental measurements and two-dimensional (2-D) device simulations are used to investigate the operating principles of a direct tunneling RAM (DT-RAM) cell. DT-RAM targets memory applications in which manufacturability, scalability, low-power, high-density, and long retention times are important considerations.

A Highly Scalable Capacitor-Less Cell Having a Doubly Gated Vertical Channel

“…A thin body thickness also increases body coefficient so that it can enhance sensing margin between the ''0'' state and the ''1'' state. 4,9) As shown in Fig. 7, a reduced body thickness diminishes the DIBL effect and widens the sensing margins.…”

“…This selfconvergent process is very useful for avoiding a disturbance of Write ''0'' operation. 4) The state of the cell is decided by sensing the drain current during the read operation. If holes are stored in the body, the threshold voltage will be reduced, and the drain current will increase from its initial state.…”

“…The double-gate DRAM (DG-DRAM) cell was proposed as a more scalable design for capacitor-less DRAM. 3,4) Unlike conventional double-gate logic transistors, the two gates in double-gate DRAM cells are not electrically connected. This structure permits an electrically induced floating body to occur within a thin fully depleted body.…”