Directed Assembly of One-Dimensional Nanostructures into Functional Networks

Huang, Yu; Duan, Xiangfeng; Wei, Qiou; Lieber, Charles M.

doi:10.1126/science.291.5504.630

Cited by 2,115 publications

(1,488 citation statements)

References 24 publications

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“…The realization of flexible and transparent NWTs could also enable high-resolution and lowpower consumption products such as head-up displays. Although challenges remain in the precise control of nanowire positions and orientations on large-scale substrates for NWT integration, promising advances have recently been reported [42][43][44][45] . For example, one report has demonstrated greater than 90% yield for the assembly of single-walled carbon nanotubes in desired positions 42 .…”

Section: Resultsmentioning

confidence: 99%

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics

et al. 2007

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Section: Resultsmentioning

confidence: 99%

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics

et al. 2007

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“…7,8 These unique electrical properties and the intrinsically miniaturized dimensions of NW and carbon nanotube building blocks may facilitate the continuation of Moore's law and the evolutionary quest for ever faster and smaller electronics well into the future. More uniquely, the capability of assembling high-performance NW building blocks with diverse functional properties could enable novel circuit concepts such as 3D integrated electronics, 9 where 3D structure arises from sequential assembly [10][11][12] of NWs into vertically stacked device layers.…”

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confidence: 99%

Layer-by-Layer Assembly of Nanowires for Three-Dimensional, Multifunctional Electronics

et al. 2007

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We report a general approach for three-dimensional (3D) multifunctional electronics based on the layer-by-layer assembly of nanowire (NW) building blocks. Using germanium/silicon (Ge/Si) core/shell NWs as a representative example, ten vertically stacked layers of multi-NW fieldeffect transistors (FETs) were fabricated. Transport measurements demonstrate that the Ge/Si NW FETs have reproducible high-performance device characteristics within a given device layer, that the FET characteristics are not affected by sequential stacking, and importantly, that uniform performance is achieved in sequential layers 1 through 10 of the 3D structure. Five-layer single-NW FET structures were also prepared by printing Ge/Si NWs from lower density growth substrates, and transport measurements showed similar high-performance characteristics for the FETs in layers 1 and 5. In addition, 3D multifunctional circuitry was demonstrated on plastic substrates with sequential layers of inverter logical gates and floating gate memory elements. Notably, electrical characterization studies show stable writing and erasing of the NW floating gate memory elements and demonstrate signal inversion with larger than unity gain for frequencies up to at least 50 MHz. The ability to assemble reproducibly sequential layers of distinct types of NW-based devices coupled with the breadth of NW building blocks should enable the assembly of increasing complex multilayer and multifunctional 3D electronics in the future.Over the past several years, semiconductor NWs 1,2 and carbon nanotubes 3 have been actively explored as the potential materials for future electronic components. These chemically derived single-crystalline nanostructures present unique advantages over conventional semiconductors, as they enable integration of high-performance device elements onto virtually any substrate 4-6 with scaled on-currents and switching speeds higher than state-of-the-art planar Si structures. 7,8 These unique electrical properties and the intrinsically miniaturized dimensions of NW and carbon nanotube building blocks may facilitate the continuation of Moore's law and the evolutionary quest for ever faster and smaller electronics well into the future. More uniquely, the capability of assembling high-performance NW building blocks with diverse functional properties could enable novel circuit concepts such as 3D integrated electronics, 9 where 3D structure arises from sequential assembly 10-12 of NWs into vertically stacked device layers.Indeed, there has been considerable interest in multilayer electronics, as they offer a more efficient interconnection and processing of digital information. [13][14][15] However, materials-and fabrication-related challenges have presented major obstacles in achieving truly 3D integrated circuits based on the conventional Si CMOS technology, and the need for a new technology remains critical. Here, we report the monolithic integration of individual and parallel arrays of crystalline NWs as multifunctional and multilayer circuits...

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“…Moreover, precise deposition of NWs with respect to device electrodes remains very challenging, and additional fabrication efforts are required, for example, to guide NWs through microfluidic channels to deposit across the device electrodes, 17 still with no control of the NWs lateral alignment. Recent progress in dielectrophoresis (DEP) alignment and deposition of NWs has demonstrated both large-area compatible processing and high accuracy isolated nanowires placement associated with the strongest DEP force exerted on the NW in the vicinity of the electrodes.…”

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confidence: 99%

Simultaneous Tunable Selection and Self-Assembly of Si Nanowires from Heterogeneous Feedstock

Constantinou¹,

Rigas

Castro

et al. 2016

ACS Nano

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Semiconducting nanowires (NWs) are becoming essential nano-building blocks for advanced devices from sensors to energy harvesters, however their full technology penetration requires large scale materials synthesis together with efficient NW assembly methods. We demonstrate a scalable one-step solution process for the direct selection, collection and ordered assembly of silicon NWs with desired electrical properties from a poly-disperse collection of NWs obtained from a Supercritical Fluid-Liquid-Solid growth process. Dielectrophoresis (DEP) combined with impedance spectroscopy provides a selection mechanism at high signal frequencies (>500 kHz) to isolate NWs with the highest conductivity and lowest defect density. The technique allows simultaneous control of five key parameters in NW assembly: selection of electrical properties, control of NW length, placement in pre-defined electrode areas, highly preferential orientation along the device channel and control of NWs deposition density from few to hundreds per device. Direct correlation between DEP signal frequency and deposited NWs conductivity is directly confirmed by field-effect transistor and conducting-AFM data. Fabricated NW transistor devices demonstrate excellent performance with up to 1.6 mA current, 106-107 on/off ratio and hole-mobility of 50 cm2 V-1 s-1

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Directed Assembly of One-Dimensional Nanostructures into Functional Networks

Cited by 2,115 publications

References 24 publications

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics

Layer-by-Layer Assembly of Nanowires for Three-Dimensional, Multifunctional Electronics

Simultaneous Tunable Selection and Self-Assembly of Si Nanowires from Heterogeneous Feedstock

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