Discrete-Time Modeling of High Power Asymmetric Half-Bridge LED Constant-Current Driver Controlled by Digital Current Mode

Qiao, Zhiyong; Wang, Shunli; Wang, Ronghai; Shi, Yile; Xiong, Xingchuang; Zhang, Nan; Liu, Zhigui

doi:10.1109/access.2021.3059961

Cited by 4 publications

(1 citation statement)

References 24 publications

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“…For the DPCC inductance current inner loop, the Zdomain transfer function can be obtained from the current error to the duty cycle as shown in Formula (32): are small signal discrete models of AHB, which can be obtained by bilinear transformation from the average small signal model provided in the literature [27] or derived by the discrete-time modeling method [28]. Accordingly, the loop gains of inductor current inner loop and LED current outer loop controlled by DPCC can be obtained as shown in Formulas (33) and (34):…”

Section: Bdiscrete Small Signal Modeling For Dpccmentioning

confidence: 99%

Digital Predictive Current-Mode Control for Asymmetrical Half-Bridge LED Constant-Current Driver

et al. 2022

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In this paper, we propose three advanced digital predictive current-mode control (DPCC) algorithms based on a simplified estimation method of duty cycle lost time for asymmetric half-bridge (AHB) LED constant-current driver. They are the digital predictive peak current mode control(DPPCC) algorithm based on leading-edge modulation, the digital predictive quasi-valley current mode control(DPqVCC) algorithm based on trailing-edge modulation, and the digital predictive quasi-average current mode control(DPqACC) algorithm based on double-edge modulation. Simulation and experimental results demonstrate that the three DPCC algorithms can effectively offset the effect of delay on digital control performance, which confirms the superiority of DPqACC. When the DPqACC is applied, the seriesload-jump transition times are below 4.5 ms, the maximum load adjustment rate is 0.5%/ V, and the output current can be tuned continuously between 0.3 A and 4.5 A with the longest transition time of 1 ms. Moreover, the three DPCC algorithms are capable of compensating for low-frequency ripples due to the rapid regulation speed of the inner loop. With the electrolytic capacitance removed without additional ripple compensation, the maximum peak-to-peak value of the low-frequency secondary ripple is 0.1163 A (2.91%) when the input isV and the output is 4 A. This approach provides an excellent solution for the digital design of low-ripple AC-DC LED constant-current drivers without electrolytic capacitance.INDEX TERMS asymmetric half-bridge; constant-current driver; estimation of duty cycle lost time; predictive quasi-average current mode; digital predictive current-mode control

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Section: Bdiscrete Small Signal Modeling For Dpccmentioning

confidence: 99%