Disruptive ultra-low-leakage design techniques for ultra-low-power mixed-signal microsystems

Abstract

In this paper, we describe applications of a disruptive ultra-low-leakage design technique for drastically reducing the off current in CMOS mixed analog-digital microsystems without compromising the functional performance. The technique is based on a pair of source-connected n-and p-MOS transistors, automatically biasing the stand-by gate-tosource voltage of the nMOSFET at a negative voltage and that of the pMOSFET at a positive level, thereby pushing the off current towards its physical limits. Playing with gate and drain connections, we have created a family of ULP basic blocks : a 2terminal diode, a 3-terminal transistor and a voltage follower. Using these blocks, we have developed a 7-transistor SRAM cell and an MTCMOS latch with record low stand-by leakage but still high speed performance, highly-efficient power-management units for RF and PV energy harvesting and a microwatt interface for implanted capacitive sensors.Index Terms-Ultra low leakage, Ultra low power, analog and digital CMOS circuits, logic, SRAM, power management, energy harvesting, voltage reference, SOI technology.978-1-61284-647-7/11/$26.00 ©2011 IEEE

Ultra-low-power diodes using junctionless nanowire transistors

“…From these curves it is possible to note that W fin,P increase causes the rise of leakage current, due to the increase of the pMOS JNT threshold voltage (V TP ). In reverse mode, both transistors in the ULP diode must work in weak conduction level regime [8]. As V TP is increased, the pMOS leaves weak conduction level and its resistance is decreased, such that practically all the bias voltage applied to the ULP diode drops across the nMOS only, leading to a I D -V D characteristic similar to that a standard nMOS diode, but consuming larger area, which is undesirable.…”

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“…The support technology will be standard 0.35µm CMOS technology which provides low current leakage [Flandre (2011)] and so consumption reduction.…”