Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction

A survey of architectural techniques for improving cache power efficiency

“…without die-stacking) cache and also block-based and page-based 3D stacked DRAM cache designs. [19], [31], [39], [42], [45], [52], [53], [79] state-destroying [13], [20], [23]- [25], [29], [43], [70], [80]- [86] either or both [30], [41], [87], [88] Reconfig. granularity way-level [20], [52], [53], [56], [89]- [93] set-level (or bank-level) [43], [92] hybrid (set and way) level [23], [81], [94] cache block-level [13], [29], [31], [41], [42], [45], [78]- [80], [84], [88] cache sub-block level [86], cache color level [24]- [26] cache sub-array level [82] Reconfig.…”

“…State-destroying techniques (e.g., [44]) do not preserve the state of the turned-off block, but generally save more energy in the low-power states than the state-preserving techniques. Several microarchitecture level techniques utilize state-preserving leakage control (e.g., [19], [31], [39], [42], [45], [52], [53], [79]), while others employ state-destroying leakage control (e.g., [13], [20], [23]- [25], [29], [43], [70], [80]- [86]). Some researchers have proposed techniques which work with either of or both of state-preserving or statedestroying leakage control mechanism [30], [41], [87], [88].…”

Power gating strategies on GPUs

“…Compared to a previous study [Duarte et al 2002] that estimated the energy and performance overheads of power gating on various types of functional units, we believe that the break-even time and the wake-up delay assumed for the shader cluster are likely to be overestimated; as a result, the leakage reduction of PSS reported in the next section is not inflated. For DGP evaluation, because the largest component in those stages is the post-transform vertex cache (approximately 64KB), we assume that the break-even time of power gating the fixed-function geometry units is 80 cycles by scaling the values in Kalla et al [2006] and that the wake-up delay is 100 cycles, which is the same as a shader cluster. Because the time-out power gating technique exploits finer granularity in the idle time, the break-even time and the wake-up delay could have a significant impact on the amount of leakage reduction achieved.…”

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

“…Other techniques reconfigure cache using computer software [43], while some techniques predict the program behaviour [3,41,42,[44][45][46]. Some techniques deal with instructions in the cache [3,15,16,41,[47][48][49][50][51][52]. Some techniques seek to leverage unused cache block words in order to reduce dynamic power consumption [18,36,53].…”