Distributed arithmetic architectures for FIR filters-A comparative review

Jyothi, Grande Naga; Sridevi, Sriadibhatla

doi:10.1109/wispnet.2017.8300250

Cited by 32 publications

(11 citation statements)

References 24 publications

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“…NagaJyothi and Sridevi [20] Mohanty and Meher [22] proposed a novel common DA formulation for the convolution and correlation and a new LUT updating technique. The LUT size and adders are reduced by this new approach.…”

Section: Related Workmentioning

confidence: 99%

Implementation of Efficient FIR Filter Architectures using Distributed Arithmetic Computation for Digital Channelizer of SDR

Bhadavath

Livinsa

2022

Preprint

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Always an efficient and low complexity reconfigurable filter architecture is required for the channel filters of digital channelizer in Software Defined Radio (SDR). In this paper, a block-based reconfigurable FIR filter is proposed using Distributed Arithmetic (DA) Technique. The complexity of the conventional multiplier is replaced with the DA multiplication process and the throughput of the entire filter is increased by block processing. Memory reuse is also achieved in the proposed direct form systolic FIR filter architecture due to parallel processing. The different bandwidth filters and the corresponding coefficients are stored in the LUTs concerning different channels of the digital channelizer. The proper channel selection is used to choose an appropriate filter and partial products are generated using Offset Binary Coding (OBC). Next, the multiplication process is done by the proposed decomposed LUT-based DA technique in the processing blocks of the filter. The proposed filter is coded by Verilog and synthesized by ASIC-based tools from Cadence in 45 nm CMOS technology. The performance parameters such as area, delay, power consumption, ADP, and PDP are evaluated and compared with the state-of-the-art works. The ADP and PDP values are saved by 44.1% and 30% by the proposed OBC-DA-based filter architecture than the conventional DA-based filter architecture, respectively.

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Section: Related Workmentioning

confidence: 99%

Implementation of Efficient FIR Filter Architectures using Distributed Arithmetic Computation for Digital Channelizer of SDR

Bhadavath

Livinsa

2022

Preprint

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“…DA architecture was more useful in decision feedback equalizer [4], image enhancement [5], for removing noises in the ECG signal analysis. In all these the DA based FIR filter plays a key role [6][7][8][9]. The basic block of GDI is explained in Fig.…”

Section: Literature Surveymentioning

confidence: 99%

High Speed Low Area DA Based FIR Filter Using EGDI Adder

Vijetha¹,

Naik²

2022

IJIE

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In this paper we proposed a novel enhanced gate diffusion (EGDI) adder is designed and is implemented in Distributed Arithmetic (DA) based Finite Impulse Response (FIR) filter. Generally multipliers, adders and shift accumulators are the basic blocks present in the FIR filters. The hardware architecture of multipliers is very high. To get rid of this, multiplier less architecture are needed in FIR filter. So Distributed Arithmetic architecture place a key role in FIR filters which will occupy less area and increase the speed. To reduce the area further the adders in DA are designed using enhanced gate diffusion (EGDI) which increases the operation speed of FIR filter and at same time the area will be decreased. The proposed design is synthesized and implemented in Synapsis design compiler tool. The area, power delay product, frequency, area delay product and power of the proposed design are calculated. When we observe the synthesis results, the proposed design has 15% high frequency rate when compare with the existing design. Also the proposed design is more useful in signal processing applications like decision feed-back equalizer.

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“…The third approach is to encode the binary inputs with 2's complement, CSD or the more common OBC scheme to reduce the memory size by half. Design choice also involves the LUT-less approach which replaces the memory units with multiplexers, hence more combinational logic is involved [25]. The major problem is that whenever we move towards the implementation of higher order filters, either latency or memory shows expensive results.…”

Section: Literature Reviewmentioning

confidence: 99%

A Novel Multiplier-Less LMS Adaptive Filter Design Based on Offset Binary Coded Distributed Arithmetic

et al. 2021

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Multiply-Accumulate (MAC) operation is the backbone of Least Mean Squares (LMS) digital adaptive filters. Implementing LMS on hardware platform as a Fully Dedicated Architecture (FDA) multiplier becomes bottleneck for higher order filters, prompting high area, cost and power requirements and hence renders the design unsuited for practical implementation. In this paper, we have proposed a composite design that makes use of Distributed Arithmetic (DA) to replace the bottleneck multiplier with memory units that store Partial Products (PPs) to emulate multiplication. The depth of these memory units tends to exponentially grow as the filter order rises. To manage that, we have used Half Memory algorithm (HM) and Offset Binary Coding (OBC) to refine the structure of PPs such that the memory size is reduced at least by a factor of 4 for the same filter order. The proposed design improves system's Throughput, Critical Path Delay, Power Consumption and FPGA Resource Utilization. However, it introduces Latency in both the output and update segments of the LMS algorithm. To provide an option between resource utilization and latency, we have suggested a mechanism to halve the originally produced latency by the Parallel Processing of input bit steam w.r.t even and odd bits. Moreover, we have also proposed a method that reduces the latency of update module at the slight expense of other design attributes. The fundamental structure of the proposed design is flexible owing to the dynamic memory structure as well as the option to choose between latency and resource minimization. Simulations have been carried out in Xilinx Vivado and conclusions have been drawn by comparing both FDA and DA based designs. Results for a 16-tap filter indicate a remarkable improvement in Throughput, Area Utilization and Power Consumption by 18%, 5% and 3.5% respectively at the expense of 4× escalated latency. The Half Latency method allowed the latency to drop 2× but with slightly elevated power and area attributes.

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Distributed arithmetic architectures for FIR filters-A comparative review

Cited by 32 publications

References 24 publications

Implementation of Efficient FIR Filter Architectures using Distributed Arithmetic Computation for Digital Channelizer of SDR

Implementation of Efficient FIR Filter Architectures using Distributed Arithmetic Computation for Digital Channelizer of SDR

High Speed Low Area DA Based FIR Filter Using EGDI Adder

A Novel Multiplier-Less LMS Adaptive Filter Design Based on Offset Binary Coded Distributed Arithmetic

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