Distributed Modeling of Layout Parasitics in Large-Area High-Speed Silicon Power Devices

Biondi, T.; Greco, Giuseppe; Allia, M.C.; Liotta, S.F.; Bazzano, Gaetano; Rinaudo, Salvatore

doi:10.1109/tpel.2007.904241

Cited by 23 publications

(11 citation statements)

References 42 publications

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“…The effective resistances required by Equation 1 are then determined by solving the matrix equation that results. This process is similar to that outlined in [14].…”

Section: Layout To Device Parasitic Parameterssupporting

confidence: 56%

Optimization of Integrated Transistors for Very High Frequency DC–DC Converters

Sagneri¹,

Anderson

Perreault

2013

IEEE Trans. Power Electron.

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Abstract-This document presents a method to optimize integrated LDMOS (Lateral Double-Diffused MOSFET) transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is developed. Device parameters are related to layout geometry and the resulting layout vs. loss tradeoffs are illustrated. A method of finding an optimal layout for a given converter application is developed and experimentally verified in a 50 MHz converter, resulting in a 54% reduction in power loss over a hand-optimized device. It is further demonstrated that hot-carrier limits on device safe operating area may be relaxed under soft switching, yielding significant further loss reduction. A device fabricated with 3 um gate length in 20-V design rules is validated at 35-V, offering reduced parasitic resistance and capacitance as compared to the 5.5 um device. Compared to the original design, loss is up to 75% lower in the example application.

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“…The effective resistances required by Equation 1 are then determined by solving the matrix equation that results. This process is similar to that outlined in [14].…”

Section: Layout To Device Parasitic Parameterssupporting

confidence: 56%

Optimization of Integrated Transistors for Very High Frequency DC–DC Converters

Sagneri¹,

Anderson

Perreault

2013

IEEE Trans. Power Electron.

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“…The simulated device is a silicon power MOSFET, which was calibrated according to the prototype developed by ST microelectronics [1]. The device is powered by means of parallel fingers which are placed at a distance of 2.4µm.…”

Section: Simulation Methodologymentioning

confidence: 99%

“…Large area power MOSFETs are typically affected by non-uniformity of biasing, due to the delay in signal propagation [1]. This phenomenon causes a dependence of the self-heating effects on the device position.…”

Section: Introductionmentioning

confidence: 99%

Numerical simulation and modeling of thermal transient in silicon power devices

Magnone¹,

Fiegna²,

Greco³

et al. 2013

Solid-State Electronics

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“…Many layout styles, including multi-fingers, waffle, overlapping circular gate, wave, and diamond styles have been developed. However, the uniform distribution of the load current is still difficult to guarantee [ 9 ]. Figure 1 shows an infrared thermal photograph of a 45 V N-type power MOS with a power dissipation of 1 W. The temperature at the substrate ring is 53.3–55.2 °C, and that at the top metal above the transistor channel is 42.4–46.1 °C.…”

Section: Introductionmentioning

confidence: 99%

LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs

Lin

2017

Sensors

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This paper presents a method of thermal balancing for monolithic power integrated circuits (ICs). An on-chip temperature monitoring sensor that consists of a poly resistor strip in each of multiple parallel MOSFET banks is developed. A temperature-to-frequency converter (TFC) is proposed to quantize on-chip temperature. A pulse-width-modulation (PWM) methodology is developed to balance the channel temperature based on the quantization. The modulated PWM pulses control the hottest of metal-oxide-semiconductor field-effect transistor (MOSFET) bank to reduce its power dissipation and heat generation. A test chip with eight parallel MOSFET banks is fabricated in TSMC 0.25 μm HV BCD processes, and total area is 900 × 914 μm2. The maximal temperature variation among the eight banks can reduce to 2.8 °C by the proposed thermal balancing system from 9.5 °C with 1.5 W dissipation. As a result, our proposed system improves the lifetime of a power MOSFET by 20%.

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Distributed Modeling of Layout Parasitics in Large-Area High-Speed Silicon Power Devices

Cited by 23 publications

References 42 publications

Optimization of Integrated Transistors for Very High Frequency DC–DC Converters

Optimization of Integrated Transistors for Very High Frequency DC–DC Converters

Numerical simulation and modeling of thermal transient in silicon power devices

LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs

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