Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory Array

Wang, Luzhou; Sano, Kentaro; Yamamoto, Satoru

doi:10.1007/978-3-642-28365-9_3

Cited by 12 publications

(5 citation statements)

References 12 publications

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“…Darkroom [31] generates optimized HDL for image processing codes, and the popular image processing framework Halide [32] has been extended to support FPGAs [87]. Luzhou et al [46] propose a framework for generating stencil codes for FPGAs. These frameworks rely on optimizations such as delay buffering, streaming and replication, which we cover here.…”

Section: Related Workmentioning

confidence: 99%

Transformations of High-Level Synthesis Codes for High-Performance Computing

Licht

Besta

Meierhans

et al. 2021

IEEE Trans. Parallel Distrib. Syst.

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Specialized hardware architectures promise a major step in performance and energy efficiency over the traditional load/store devices currently employed in large scale computing systems. The adoption of high-level synthesis (HLS) from languages such as C/C++ and OpenCL has greatly increased programmer productivity when designing for such platforms. While this has enabled a wider audience to target specialized hardware, the optimization principles known from traditional software design are no longer sufficient to implement high-performance codes, due to fundamentally distinct aspects of hardware design, such as programming for deep pipelines, distributed memory resources, and scalable routing. Fast and efficient codes for reconfigurable platforms are thus still challenging to design. To alleviate this, we present a set of optimizing transformations for HLS, targeting scalable and efficient architectures for high-performance computing (HPC) applications. Our work provides a toolbox for developers, where we systematically identify classes of transformations, the characteristics of their effect on the HLS code and the resulting hardware (e.g., increases data reuse or resource consumption), and the objectives that each transformation can target (e.g., resolve interface contention, or increase parallelism). We show how these can be used to efficiently exploit pipelining, on-chip distributed fast memory, and on-chip streaming dataflow, allowing for massively parallel architectures. To quantify the effect of our transformations, we use them to optimize a set of throughput-oriented FPGA kernels, demonstrating that our enhancements are sufficient to scale up parallelism within the hardware constraints. With the transformations covered, we hope to establish a common framework for performance engineers, compiler developers, and hardware developers, to tap into the performance potential offered by specialized hardware architectures using HLS.

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Section: Related Workmentioning

confidence: 99%

Transformations of High-Level Synthesis Codes for High-Performance Computing

Licht

Besta

Meierhans

et al. 2021

IEEE Trans. Parallel Distrib. Syst.

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“…There are some works that focus on the adaptation of stencil computations to the FPGA architecture using an OpenCL-based solution. In Waidyasooriya et al (2017), Sano et al (2014), Luzhou et al (2012), Okina et al (2016), and Waidyasooriya and Hariyama (2016) the authors propose libraries containing basic stencils, including Jacobi (in all the papers excluding Waidyasooriya and Hariyama, 2016) and FDTD (in Waidyasooriya and Hariyama, 2016;Waidyasooriya et al, 2017). The results show that the FPGA is a promising architecture for the presented algorithms.…”

Section: Related Workmentioning

confidence: 99%

CFD code adaptation to the FPGA architecture

Rojek¹,

Halbiniak²,

Kuczynski

2020

The International Journal of High Performance Computing Applica

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For the last years, we observe the intensive development of accelerated computing platforms. Although current trends indicate a well-established position of GPU devices in the HPC environment, FPGA (Field-Programmable Gate Array) aspires to be an alternative solution to offload the CPU computation. This paper presents a systematic adaptation of four various CFD (Computational Fluids Dynamic) kernels to the Xilinx Alveo U250 FPGA. The goal of this paper is to investigate the potential of the FPGA architecture as the future infrastructure able to provide the most complex numerical simulations in the area of fluid flow modeling. The selected kernels are customized to a real-scientific scenario, compatible with the EULAG (Eulerian/semi-Lagrangian) fluid solver. The solver is used to simulate thermo-fluid flows across a wide range of scales and is extensively used in numerical weather prediction. The proposed adaptation is focused on the analysis of the strengths and weaknesses of the FPGA accelerator, considering performance and energy efficiency. The proposed adaptation is compared with a CPU implementation that was strongly optimized to provide realistic and objective benchmarks. The performance results are compared with a set of server CPUs containing various Intel generations, including Intel SkyLake-based CPUs as Xeon Gold 6148 and Xeon Platinum 8168, as well as Intel Xeon E5-2695 CPU based on the IvyBridge architecture. Since all the kernels belong to the group of memory-bound algorithms, our main challenge is to saturate global memory bandwidth and provide data locality with the intensive BRAM (Block RAM) reusing. Our adaptation allows us to reduce the performance per watt up to 80% compared to the CPUs.

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“…However, overlapped tiling over 2D data significantly increases both the amount of redundant computation and extra I/O. Luzhou et al [6] also use a form of tiling to implement stencil computations on FPGA. However, the tiling applied in this work is only for the spatial dimensions.…”

Section: Stencil Computations On Fpgasmentioning

confidence: 99%

“…Approach vs. characteritics non-tiled on-chip [6] non-tiled off-chip [5], [9] partial oblique tiling [10] full oblique tiling (ours) overlapped tiling [7] Domain size scalability…”

Section: B Overview Of the Execution Datapathmentioning

confidence: 99%

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One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs

Deest

Yuki²,

Rajopadhye³

et al. 2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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We generate a family of FPGA stencil accelerators targeting emerging System on Chip platforms, (e.g., Xilinx Zynq or Intel SoC). Our designs come with design knobs to explore trade-offs. We also propose performance models to hone in on the most interesting design points, and show how they accurately lead to optimal designs. The optimal choice depends on problem sizes and performance goals. I. INTRODUCTIONIterative stencil computations arise in many application domains, ranging from medical imaging to numerical simulation. Since they are computationally demanding, a large body of work addressed the problem of parallelizing and optimizing stencils for multi-cores, GPUs, and FPGAs.Earlier attempts targeting FPGAs showed that the performance of such accelerators is a complex interplay between the raw FPGA computing power, the amount of on-chip memory, and the performance of the external memory system [1]- [8]. They also illustrate different application requirements. For example, in the context of embedded vision, designers often seek the cheapest design achieving real-time performance constraints (e.g., 4K@60fps). In an exascale context, they may want to maximize performance (measured in ops-persecond) for a given FPGA board, while maintaining power dissipation to a minimum. Therefore, we explore a family of design options that can accommodate a large set of constraints, by exposing trade-offs between computing power, bandwidth requirements, and FPGA resource usage. We focus on system-level issues. Our aim is not to provide hand-optimized FPGA implementations. We have developed a code generator that produces HLS-optimized C/C++ descriptions of accelerator instances, leaving low-level decisions to the HLS back-end.Our designs build upon the tiling transformation, that we use to balance on-chip memory cost and off-chip bandwidth. The design space we explore can be characterized by the following design knobs.

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Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory Array

Cited by 12 publications

References 12 publications

Transformations of High-Level Synthesis Codes for High-Performance Computing

Transformations of High-Level Synthesis Codes for High-Performance Computing

CFD code adaptation to the FPGA architecture

One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs

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