DONUT: A Double Node Upset Tolerant Latch

Eftaxiopoulos, Nikolaos; Axelos, Nicholas; Pekmestzi, Kiamal

doi:10.1109/isvlsi.2015.72

Cited by 69 publications

(54 citation statements)

References 30 publications

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“…(2) As is presented in Table 2, the proposed HLDUT latch saves 191.2%, 53.6%, 80.2%, 760.7%, 470.0%, 270.8%, 342.9% and 8.8% delay compared with the traditional, HiPeR [7], HLR-CG1 [8], DNCS [13], CLCT [14], Delta DICE [15], DONUT [16] and DNURL [17], respectively. Compared with other DU (let alone SU) tolerant latches, the proposed HLDUT latch is also a power-efficient design, even though it exhibits 25.6% and 27.6% power penalty over the traditional and HiPeR [7].…”

Section: Discussionmentioning

confidence: 98%

“…Well isolation, guard rings and layout techniques were utilized to solve the multiple upsets caused by charge sharing, but benefits of these techniques are quite limited [9,10]. In order to solve this severe problem, researchers have proposed plenty of latches which can effectively tolerate the DUs [11][12][13][14][15][16][17]. The latch designed in [12] employed a modified triple path dual-interlocked storage cell (TPDICE) [11] and Muller C-element (MCE), acquiring better tolerance.…”

Section: Introductionmentioning

confidence: 99%

“…However, the latch in [14] was not fully SEDU tolerant in the circuit design level, and further, layout technique was used to harden the latch. The Delta DICE in [15], DONUT (Double Node Upset Tolerant) in [16], and DNURL (Double-Node-Upset-Resilient Latch) in [17] were derived by the applications of feedback loop. However, it is worth noticing that these latches were carried out with large cost penalties in terms of delay, power consumption and area.…”

Section: Introductionmentioning

confidence: 99%

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A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design

et al. 2018

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Single event double upsets (SEDUs) caused by charge sharing have been an important contributor to the soft error in integrated circuits. Most of the up-to-date double-upset (DU) tolerant latches suffer from high costs in terms of delay, power and area. In this paper, we propose a novel high-performance low-cost double-upset tolerant (HLDUT) latch. Simulation waveforms have validated the double-upset tolerance of the proposed latch. Besides, detailed comparisons demonstrate that our design saves 805.24% delay-power-area product (DPAP) on average compared with other considered up-to-date double-upset tolerant latches, which means the proposed latch is a promising candidate for future highly reliable low-cost applications.

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Section: Discussionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design

et al. 2018

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“…The DICE has good trade-off between soft error tolerant capability and performance and then many researchers have studied its extension. For example, F-DICE [6], Delta DICE [7] and DONUT latches [8], [9] have multiple-nodeupset (MNU) tolerant capability while the original DICE is capable of tolerating only SNUs. The DF-DICE [10] and the FF of [11] is capable of tolerating single-event-transients (SETs) as well as SEUs by using delay elements.…”

Section: Introductionmentioning

confidence: 99%

Master-Slave FF Using DICE Capable of Tolerating Soft Errors Occurring Around Clock Edge

Namba

2020

IEICE Trans. Inf. & Syst.

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This letter reveals that an edge-triggered master-slave flipflop (FF) using well-known soft error tolerant DICE (dual interlocked storage cell) is vulnerable to soft errors occurring around clock edge. This letter presents a design of a soft error tolerant FF based on the master-slave FF using DICE. The proposed design modifies the connection between the master and slave latches to make the FF not vulnerable to these errors. The hardware overhead is almost the same as that for the original edge-triggered FF using the DICE.

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“…The so-called "Delta DICE" was proposed by [7], which was said to be resilient to DNU. The main disadvantage is that both Delta DICE and another structure called "DONUT" [8] are composed of 12 inverters, namely 24 transistors. The largely increased area reduces their use in practical products.…”

Section: Introductionmentioning

confidence: 99%

A Double Node Upset Tolerant Memory Cell

Liu¹,

Mao²,

Zhong³

et al. 2016

Proceedings of the 2016 4th International Conference on Advanced Materials and Information Technology Processing (AMITP 2016)

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Abstract. As we enter the deep submicron era, the steadily shrinking feature sizes make charge sharing much easier among physically adjacent nodes in integrated circuits, which ultimately results in DNU (Double Nodes Upset). In this paper, we propose a 16-transistor memory cell. Hspice simulation shows this cell maintains its original logic status under SNU (Single Node Upset) and DNU, while DICE (Dual Interlock CEll) and Quatro-10T cell may fail. Besides, the 16T cell reduces the circuit area by 33.33%, compared to the other two DNU tolerant cells, Delta DICE and DONUT.

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DONUT: A Double Node Upset Tolerant Latch

Cited by 69 publications

References 30 publications

A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design

A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design

Master-Slave FF Using DICE Capable of Tolerating Soft Errors Occurring Around Clock Edge

A Double Node Upset Tolerant Memory Cell

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