Dopant diffusion in poly gate CMOS process

The microstructure and metal-silicon work function was evaluated for polycrystalline Si (poly-Si) films ( -3500 A) implanted with BF,, with and without a CoSi, superlayer. The poly-Si implant doses were 2, 4, and 6 x lOI cm -*, activated at 800-950 "C, for various times. The work function is observed to be dependent upon the BF, dose, the anneal time, the anneal temperature, and independent of the presence of a thin CoSi, superlayer subsequently sintered on the poly-Si. The work function is not affected by additional implants into a CoSi, superlayer. The measured work function for this material is shifted to more positive values by penetration of boron from the gate, into the oxide and possibly into the substrate during a GZ 900 "C activation cycle. The major correlation of CoSi,/poly-Si interface roughness is with poly-Si grain size. The interface becomes smoother as the poly-Si grain size becomes smaller. Similarly, the maximum extent of CoSi, asperities is less for Co sintered on BF, implanted poly-Si when the poly-Si is activated at 900 "C (smaller grain size) rather than at 950 "C. Within statistical limitations of cross-section transmission electron microscopy and sensitivity limitations of Rutherford backscatterings, CoSi, asperities do not extend close enough to the (4000-A-thick) poly-Si/SiO, interface to affect complimentary metal-oxide-semiconductor device characteristics.1510

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High-performance salicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI

Sung

Kirsch

et al. 1989

IEEE Trans. Electron Devices

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A 3.3-V CMOS technology with 0.6-pm design rules in sixth-generation twin-tub CMOS (twin-tub VI) has been developed. The major features of the device in this technology are: HIPOX twin-tub structure, n+ /p' dual-type poly gate, 125-A thin gate oxide, shallow junctions, RTA activation, and thin TiSit as source/drain/gate silicide layer. Electrical measurements show good I-V characteristics, ideal low junction leakage, latchup immunity for 4.5-pm n+-to-p+ spacing, more than 6.0-V NMOSFET snapback breakdown voltage, good hot-carrier aging properties, and undetectable dopant inter-lat-era1 diffusion through a TiSi2 shunt layer of a different type of poly. The transistors have been scaled to 0.45-asd 0.40-pm effective channel length, without punchthrough at Vds = 3.6 Y for NMOS and PMOS, respectively. A 100-ps stage delay is obtained on a 101-stage CMOS ring oscillator at an operating voltage of 3.3 V.

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Dopant diffusion in poly gate CMOS process

Cited by 3 publications

References 2 publications

Negative charge induced degradation of PMOSFETS with BF ₂ -implanted p ⁺ -poly gate

Negative charge induced degradation of PMOSFETS with BF ₂ -implanted p ⁺ -poly gate

BF2 implanted polycrystalline silicon gates with and without CoSi2: Microstructure and work functions

High-performance salicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI

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Dopant diffusion in poly gate CMOS process

Cited by 3 publications

References 2 publications

Negative charge induced degradation of PMOSFETS with BF 2 -implanted p + -poly gate

Negative charge induced degradation of PMOSFETS with BF 2 -implanted p + -poly gate

BF2 implanted polycrystalline silicon gates with and without CoSi2: Microstructure and work functions

High-performance salicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI

Contact Info

Product

Resources

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Negative charge induced degradation of PMOSFETS with BF ₂ -implanted p ⁺ -poly gate

Negative charge induced degradation of PMOSFETS with BF ₂ -implanted p ⁺ -poly gate