Doping Dependent Assessment of Accumulation Mode and Junctionless FET for 1T DRAM

Ansari, Md. Hasan Raza; Navlakha, Nupur; Lin, Jyi-Tsong; Kranti, Abhinav

doi:10.1109/ted.2018.2789901

Cited by 26 publications

(19 citation statements)

References 25 publications

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“…Conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) has reached its scaling limit due to the difficulty of miniaturizing capacitors. Therefore, capacitor-less one-transistor dynamic random-access memory (1T-DRAM), which does not need complicated capacitor fabrication, has been studied as a possible replacement for 1T-1C DRAM [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. 1T-DRAM can be densely integrated because it has a small 4F 2 cell size with a silicon-on-insulator (SOI) transistor as its basic structure.…”

Section: Introductionmentioning

confidence: 99%

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

et al. 2020

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Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell’s data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell’s state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area.

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Section: Introductionmentioning

confidence: 99%

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

et al. 2020

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“…Figure 9 a shows the conduction band (CB) diagram at zero bias condition for different gate length (100 nm, 75 nm, and 50 nm). Reduction in gate length reduces the storage area for floating based memory, which reduces the retention time [ 34 , 35 , 36 , 37 , 38 , 39 ]. The operation of this synaptic transistor is based on the floating body effect, and charge trapping/de-trapping from the nitride layer.…”

Section: Resultsmentioning

confidence: 99%

Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications

2021

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This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.

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“…It is evident from the table that due to core-shell dual gate nanowire transistor achieves better retention time. The speed of the memory is estimated through write time (WT) and it is defined as the requirement of maximum time to perform the operation while current ratio (CR) is estimated through (I1/I0) [23], [28]. Core-gate helps to achieve deeper potential well compared to conventional double gate transistor, which enhance the retention of state "1" and thus, retention time of the memory [24], [30].…”

Section: Input Information Attentionmentioning

confidence: 99%

“…In comparison with Z 2 -FET [32], our results better retention time and comparable current ratio with shorter gate length. Junctionless device has shallower potential depth and lower Charge trap / de-trap carrier lifetime due to higher doping [28], [33], which are not able to achieve high retention time compared to CSDG device. In comparison with [22], [34], CSDG device achieves higher current ratio and longer retention time.…”

Section: Input Information Attentionmentioning

confidence: 99%

Core-Shell Dual-Gate Nanowire Memory as a Synaptic Device for Neuromorphic Application

Ansari

Cho²,

Lee

et al. 2021

IEEE J. Electron Devices Soc.

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In this work, a synaptic device for neuromorphic system is proposed and designed to emulate the biological behaviors in the novel device structure of core-shell dual-gate (CSDG) nanowire flash memory. Floating-body effect in the device and charge trapping/de-trapping in the nitride layer are found to be effective for short-term potentiation (STP), long-term potentiation (LTP), and long-term depression (LTD), respectively. STP realizes a temporary potentiation in the artificial neural network, and it can transit to LTP through the process of rehearsal and meaningful association. The transition takes place at the 10 th pulse in a permissibly optimized CSDG synaptic device. The proposed device shows a stronger capacitive coupling between the dual gates, which forms a deeper potential well for charge storing and achieves better memory performance metrics such as sensing margin and retention time. The series of results reveal that the synaptic memory device is applicable to neuromorphic system due to the stronger gate controllability, multi-level weight adjustability, and Si processing compatibility.

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Doping Dependent Assessment of Accumulation Mode and Junctionless FET for 1T DRAM

Cited by 26 publications

References 25 publications

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications

Core-Shell Dual-Gate Nanowire Memory as a Synaptic Device for Neuromorphic Application

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