Double electron layer tunnelling transistor (DELTT)

Abstract

We demonstrate the double electron layer tunnelling transistor (DELTT), based on the gate control of two-dimensional-two-dimensional tunnelling in a double quantum well. Unlike previously proposed resonant tunnelling transistors, the DELTT is entirely planar and can be easily fabricated in large numbers. At 1.5 K we demonstrate peak-to-background ratios of ∼ 50:1 in source-drain conductance versus gate voltage and peak-to-valley ratios of ∼ 20:1 in the source-drain current versus source-drain voltage. Using a single DELTT in series with a load resistor, we demonstrate low-power bistable memories at 1.5 K. We also demonstrate a unipolar complementary static RAM by connecting two DELTTs in series.

Coherent Interlayer Tunneling and Negative Differential Resistance with High Current Density in Double Bilayer Graphene–WSe2 Heterostructures

“…We consider J int , Δ V , the specific conductance at the resonance peak, the PVR, operating temperature, and whether or not the NDR is gate-tunable as the main metrics characterizing resonant tunneling devices. Our device characteristics are comparable to many epitaxially grown heterostructures. − While some epitaxial heterostructures show a larger PVR, they typically have a lower peak specific conductance, ,,,, and gate-tunable NDR was demonstrated only in GaAs/AlGaAs double quantum wells at temperatures lower than 170 K , (see Supporting Information). In addition, the heterostructure described here outperforms previous vdW heterostructures employing an hBN interlayer dielectric. − , …”

“…Our device characteristics are comparable to many epitaxially grown heterostructures. [30][31][32][33][34][35][36][37][38][39][40] While some epitaxial heterostructures show a larger PVR, they typically have a lower peak specific conductance 31,34,35,38,40 , and gate-tunable NDR was demonstrated only in GaAs/AlGaAs double quantum wells at temperatures lower than 170 K 35,36 (see Supporting Information). In addition, the heterostructure described here outperforms previous vdW heterostructures employing an hBN interlayer dielectric.…”

Quantum dot celluar automata‐based encoder and priority encoder circuits: Low latency and area efficient design

“…Thus, it is required to replace the CMOS technology by a new technology, which can overcome all the limitations of CMOS transistor. In nanoscale, multiple new technologies are available such as, tunnel field‐effect transistor, 6 single electron transistor, quantum dot cellular automata (QCA), and so on. Among these technologies, QCA is a transistorless technology, 7‐9 which is SCEs immune.…”