Double Node Upsets Hardened Latch Circuits

Li, Yuanqing; Wang, Haibin; Yao, Suying; Yan, Xi; Gao, Zhiyuan; Xu, Jiangtao

doi:10.1007/s10836-015-5551-3

Cited by 69 publications

(77 citation statements)

References 19 publications

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“…This section reviews typical examples of SNU, DNU and/or TNU hardened latch designs as shown in Fig. 2 including the FEedback Redundant SNU-Tolerant (FERST) [10], RFC [15], the so-called HRPU [16], Double-Node Charge Sharing (DNCS) [17], Double-Node Upset Resilient (DNUR) [18], Non-Temporally Hardened LaTCH (NTHLTCH) [19] and TNU Hardened Latch (TNUHL) [1].…”

Section: Typical Latch Designsmentioning

confidence: 99%

“…For fair comparisons, the proposed latch designs and typ-ical SNU/DNU/TNU hardened latch designs, namely the FERST [10], RFC [15], HRPU [16], DNCS [17], DNUR [18], NTHLTCH [19] and TNUHL [1] were designed in the same 22nm CMOS technology using the predictive technology model (PTM) in [23]. The supply voltage Vdd was set to 0.8V.…”

Section: Comparisonsmentioning

confidence: 99%

“…Radiation hardening by design (RHBD) is one of the most effective techniques to mitigate soft errors. In the last decade, researchers have mostly focused on the radiation hardening for memory cells [4,5], flip-flops [6,7] and latches [1,[8][9][10][11][12][13][14][15][16][17][18][19][20][21] using RHBD techniques like multiplemodular redundancy, temporal redundancy, and so on. This paper mainly focuses on these latch designs.…”

Section: Introductionmentioning

confidence: 99%

“…This paper mainly focuses on these latch designs. In these latch designs, some are only SNU-hardened [8][9][10][11][12][13][14][15] and some are simultaneously hardened for both SNU and DNU [16][17][18][19][20][21]. As far as we know, there is currently only one design that is simultaneously hardened for SNU, DNU and TNU [1].…”

Section: Introductionmentioning

confidence: 99%

“…Some are completely SNU self-recoverable, such as the designs referred as HLR-CG1/CG2 in [11] and the self-Recoverable, Frequency-aware and Cost-effective (RFC) design in [15]. Among these DNU-hardened latch designs, some are only partially DNU-hardened [16] and some are completely DNU-hardened [17][18][19][20][21], in which the designs in [18][19][20][21] are completely DNU self-recoverable. As for currently the only one design in [1] that completely tolerates any TNU, there are some problems, such as not being completely DNU self-recoverable and having high cost penalties.…”

Section: Introductionmentioning

confidence: 99%

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Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

Yan

Lai

Zhang

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch design is proposed. The latch mainly comprises a storage module (SM) feeding back to a 3-input C-element. The SM mainly consists of eight input-split inverters. Since the inputs of the C-element cannot be simultaneously flipped, the latch tolerates any DNU in the SM. When a single node in the SM and the output node are affected, the latch can self-recover from the DNU. Second, to completely tolerate any triple-node-upset (TNU), by replacing the C-element in the LCDNUT latch with a two-level error-interceptive module constructed from triple C-elements, a novel low cost and TNU completely tolerant (LCTNUT) latch design is proposed. Simulation results demonstrate the robustness of the proposed latches. Furthermore, due to the use of a high-speed transmission path, the clock-gating technology and fewer transistors, the proposed LCTNUT latch reduces the delay-power-area product by approximately 99.39% and has a low sensitivity to the process-voltage-and-temperature variation effects, compared with currently the only TNU completely tolerant latch design.

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Section: Typical Latch Designsmentioning

confidence: 99%

Section: Comparisonsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

Yan

Lai

Zhang

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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Low cost and high performance double‐node upset resilient latch for low orbit space applications

Kumar,

Mukherjee

2023

Circuit Theory & Apps

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SummaryThis paper proposes a double‐node upset complete resilient (DNUCR) latch to meet the requirements of low orbit space applications for high robustness, cost‐effectiveness, and high performance. With the help of its interlocked loops with multiple feedbacks consisting of C‐elements (CE), input splitting CEs, 1P‐2N and 2P‐1N elements, and inverters, the proposed DNUCR latch preserves the original data even after the radiation incident. Error injection simulations in Synopsys HSPICE show that the proposed DNUCR latch recovers from all DNUs and can withstand large amount of injected charge. The simulation outcomes further show that the proposed DNUCR latch outperforms existing DNU‐resilient latches in terms of delay, power consumption, and power–delay–area product (PDAP), with an average of 48% reduction in delay, 22% savings in power, and 60% reduction in PDAP. The proposed DNUCR latch is also found to be the best among the existing radiation‐hardened latches in terms of charge‐to‐PDAP ratio.

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Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

Yan

Cao

et al. 2021

J Electron Test

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To meet the requirements of both costeffectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

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Double Node Upsets Hardened Latch Circuits

Cited by 69 publications

References 19 publications

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

Low cost and high performance double‐node upset resilient latch for low orbit space applications

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

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