Double patterning design split implementation and validation for the 32nm node

Drapeau, Martin; Wiaux, Vincent; Hendrickx, Eric; Verhaegen, Staf; Machida, Takahiro

doi:10.1117/12.712139

Cited by 69 publications

(56 citation statements)

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“…To use double patterning, patterns in the same layer need to be decomposed into two groups, which are implemented independently [5] [15]. The pattern decomposition problem for double patterning is similar to a 2-colorability problem.…”

Section: Introductionmentioning

confidence: 99%

Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

Coskun

Kahng

Rosing

2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, uncorrelated distributions of linewidth on a chip, resulting in a 'bimodal' linewidth distribution and an increase in performance variation. [13] suggested that new physical design mechanisms could reduce harmful covariance terms that contribute to this performance variation.In this paper, we propose new bimodal-aware timing analysis and optimization methods to improve timing yield of standardcell based designs that are manufactured using DPL. Our first contribution is a DPL-aware approach to timing modeling, based on detailed analysis of cell layouts. Our second contribution is an ILP-based maximization of 'alternate' mask coloring of instances in timing-critical paths, to minimize harmful covariance and performance variation. Third, we propose a dynamic programming-based detailed placement algorithm that solves mask coloring conflicts and can be used to ensure "double patterning correctness" after placement or even after detailed routing, while minimizing the displacement of timing-critical cells with manageable ECO impact.With a 45nm library and open-source design testcases, our timing-aware recoloring and placement optimizations together achieve up to 232ps (resp. 36.22ns) reduction in worst (resp. total) negative slack, and 78% (resp. 65%) reduction in worst (resp. total) negative slack variation.

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Section: Introductionmentioning

confidence: 99%

Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

Coskun

Kahng

Rosing

2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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“…The set of stitch candidate positions is found by pattern projection, which is a similar process used in some previous works [9], [15]. Fig.…”

Section: A Pattern Projectionmentioning

confidence: 99%

“…The most popular solution for sub-22 nm node is double patterning technology (DPT) [1], [9], [17]. One of many double patterning processes is called the litho-etch-litho-etch process.…”

mentioning

confidence: 99%

Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology

Fang

Chen

Chang

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Double patterning technology (DPT), in which a dense layout pattern is decomposed into two separate masks to relax its pitch, is the most popular lithography solution for the sub-22 nm node to enhance pattern printability. Previous work focused on stitch insertion to improve the decomposition success rate. However, there exist native conflicts (NCs) which cannot be resolved by any kind of stitch insertion. A design with NCs is not DPT-compliant and may fail the decomposition, resulting in design for manufacturability redesign and longer design cycles. In this paper, we give a sufficient condition for the NC existence and propose a geometry-based method for NC prediction to develop an early-stage analyzer for DPT decomposability checking. Then, a wire perturbation algorithm is presented to fix as many NCs in the layout as possible. The algorithm is based on iterative 1-D compaction and can easily be embedded into existing industrial compaction systems. The algorithm is then further applied to further reduce the number of stitches required for the decomposition process. Experimental results show that the proposed algorithm can significantly reduce the number of NCs by an average of 85% and reduce the number of stitches by an average of 39%, which may effectively increase the decomposition success rate for the next stage.

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“…Current lithography technology applying for mass production is ArF-immersion (ArF-imm) lithography, however, the resolution is now facing the limit. Thus, to further enhance the resolution, double patterning or self-aligned double patterning techniques using ArF-imm lithography are being applied for 3x nm and 2x nm processes [1][2][3]. Although those processes overcome the resolution limit of ArF-imm lithography, there are concerns relating to the increase in process steps and cost of ownership, and the difficulty of overlay [4].…”

Section: Introductionmentioning

confidence: 99%

Perpendicularly Oriented Cylinders of Si-containing Block Copolymers by Atmospheric Thermal Annealing

Seshimo¹,

Odashima

Maeda

et al. 2016

J. Photopol. Sci. Technol.

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The directed self-assembly (DSA) of block copolymers (BCPs) can realize as one of candidates for next generation lithography. The BCPs for DSA should exhibit a high resolution, an ability to form perpendicularly oriented domains in the thin film by thermal annealing under mild condition, and a high etching selectivity. Here, we report a new Si-containing BCPs targeted to form perpendicularly oriented cylinders in thin films. The hydroxyl groups in the side chains introduced in the Si-containing block provide a good surface free energy (SFE) balance leading to the perpendicular orientation. Furthermore, this orientation can be completed in only one minute atmospheric thermal annealing at 150 °C. Oxygen plasma etching for the thin films results in the achievement of hexagonally packed cylinders.

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Double patterning design split implementation and validation for the 32nm node

Cited by 69 publications

References 0 publications

Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology

Perpendicularly Oriented Cylinders of Si-containing Block Copolymers by Atmospheric Thermal Annealing

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