Downscaling Metal—Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach

Lyu, Ren-Yuan; Shie, Bo-Shiuan; Lin, Horng−Chih; Li, Peiwen; Huang, Tiao‐Yuan

doi:10.1109/ted.2016.2646221

Cited by 15 publications

(10 citation statements)

References 21 publications

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“…The emergence of novel TFT materials such as ZnO [ 7 , 8 ], InGaZnO [ 9 ], carbon nanotube (CNT) [ 10 ], and organic materials [ 11 ] has been improving the properties of TFTs including the carrier mobility, current-carrying capacities, stability, and mechanical flexibility. The progress in scaling down TFT sizes has resulted in the design and fabrication of high performance TFTs [ 12 , 13 , 14 ]. All these efforts have shrunk the performance gap between TFT and complementary metal-oxide-semiconductor (CMOS) technologies and allowed for emerging higher frequency applications (even into the THz range) as shown in this paper.…”

Section: Introductionmentioning

confidence: 99%

Multi-Segment TFT Compact Model for THz Applications

2022

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We present an update of the Rensselaer Polytechnic Institute (RPI) thin-film transistor (TFT) compact model. The updated model implemented in Simulation Program with Integrated Circuit Emphasis (SPICE) accounts for the gate voltage-dependent channel layer thickness, enables the accurate description of the direct current (DC) characteristics, and uses channel segmentation to allow for terahertz (THz) frequency simulations. The model introduces two subthreshold ideality factors to describe the control of the gate voltage on the channel layer and its effect on the drain-to-source current and the channel capacitance. The calculated field distribution in the channel is used to evaluate the channel segment parameters including the segment impedance, kinetic inductance, and gate-to-segment capacitances. Our approach reproduces the conventional RPI TFT model at low frequencies, fits the measured current–voltage characteristics with sufficient accuracy, and extends the RPI TFT model applications into the THz frequency range. Our calculations show that a single TFT or complementary TFTs could efficiently detect the sub-terahertz and terahertz radiation.

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Section: Introductionmentioning

confidence: 99%

Multi-Segment TFT Compact Model for THz Applications

2022

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“…Recently, rapidly growing studies have reported the miniaturized OS TFTs based on different structures, such as bottom‐gate staggered, [ 17–23 ] top‐gate staggered, [ 24 ] double‐gate structures, [ 25,26 ] and specialized trench‐gate, [ 27,28 ] or vertical ones. [ 9 ] However, the normally µm‐level gate (G)‐to‐source/drain (S/D) overlaps of many reported OS TFTs [ 17,18,22,23 ] limit the integration density, incompatible with the underlying complementary metal‐oxide‐semiconductor (CMOS) tier.…”

Section: Introductionmentioning

confidence: 99%

“…Following the successful mass production of μm-level amorphous InGaZnO (a-IGZO) TFTs in large-area active-matrix displays, [14][15][16] it is highly desirable to aggressively scale down the feature size of OS transistors to a deep submicrometer or even nanometer range. Recently, rapidly growing studies have reported the miniaturized OS TFTs based on different structures, such as bottom-gate staggered, [17][18][19][20][21][22][23] top-gate staggered, [24] double-gate structures, [25,26] and specialized trench-gate, [27,28] or vertical ones. [9] However, the normally μm-level gate (G)-to-source/drain (S/D) overlaps of many reported OS TFTs [17,18,22,23] limit the integration density, incompatible with the underlying complementary metal-oxide-semiconductor (CMOS) tier.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, rapidly growing studies have reported the miniaturized OS TFTs based on different structures, such as bottom-gate staggered, [17][18][19][20][21][22][23] top-gate staggered, [24] double-gate structures, [25,26] and specialized trench-gate, [27,28] or vertical ones. [9] However, the normally μm-level gate (G)-to-source/drain (S/D) overlaps of many reported OS TFTs [17,18,22,23] limit the integration density, incompatible with the underlying complementary metal-oxide-semiconductor (CMOS) tier. Moreover, such overlap-induced parasitic capacitance may lead to severe coupling effects during the terminal voltage transition in the capacitor-less eDRAM cells, thus inevitably narrowing the sensing margin.…”

Section: Introductionmentioning

confidence: 99%

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3‐Masks‐Processed Sub‐100 nm Amorphous InGaZnO Thin‐Film Transistors for Monolithic 3D Capacitor‐Less Dynamic Random Access Memories

Zhang

et al. 2023

Adv Elect Materials

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The capacitor-less embedded dynamic random access memory (eDRAM) based on oxide semiconductor (OS) transistors exhibits a promising future and thus has lead to a growing demand for nanoscale OS thin-film transistors (TFTs). In this work, a self-aligned top-gate (SATG) amorphous InGaZnO (a-IGZO) TFT is demonstrated by using the simplest 3-masks (3M) process, and the downscaling-related issues are carefully addressed to strengthen its back-end-of-line (BEOL) compatibility and mass producibility. The gate insulator (GI) and associated interface defects of the TFTs are jointly optimized with 4-nm atomic-layer-deposited (ALD) AlO x on the pre-oxidized a-IGZO. The defects in a-IGZO channel are further manipulated with a rapid thermal anneal (RTA) in oxygen. By virtue of the strengthened gate controllability and modified channel properties, the fabricated TFT with 97-nm gate length (L g ) exhibits decent performance, such as a maximum on-state current (I ON ) of 32.4 μA μm −1 , as well as clear linear and saturation characteristics. Based on such 3M SATG a-IGZO TFTs with high device performance and inherently minimal parasitic capacitances, the developed capacitor-less eDRAM bit cell achieves a wide sensing margin and a long retention time of over 500 s. A highly manufacturable oxide TFT technology for high-performance and high-density monolithic-3D (M3D) integration is thus well established.

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“…Many works were done in fabricating and characterizing AOS TFTs with short channel length, such as using advanced e-beam lithographic patterning technique [5], proposing a new film profile engineering concept [6]- [8], or adopting new structures like vertical channel structure [9] and surrounded channel structure [10]. With the methods mentioned above, very short channel length can be obtained but along with high cost.…”

Section: Introductionmentioning

confidence: 99%

P‐1.5: Fabrication of Self‐Aligned Top‐Gate Amorphous InGaZnO Thin‐Film Transistors with Submicron Channel Length

Cao

Yang

Zhang

2019

Symp Digest of Tech Papers

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A method based on photoresist trimming technique was developed to fabricate self‐aligned top‐gate amorphous indium‐gallium‐zinc oxide (a‐IGZO) thin‐film transistors (TFTs) with submicron channel length. In this scheme, a hard mask layer was adopted to further reduce the channel length defined by the photoresist trimming process. With this method, the self‐aligned top‐gate a‐IGZO TFT with channel length of about 0.6µm is fabricated. Moreover, the fabricated device shows a field effect mobility of 6.8 cm2/Vs, a subthreshold swing of 0.29V/decade, and high ON/OFF current ratio up to 108.

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Downscaling Metal—Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach

Cited by 15 publications

References 21 publications

Multi-Segment TFT Compact Model for THz Applications

Multi-Segment TFT Compact Model for THz Applications

3‐Masks‐Processed Sub‐100 nm Amorphous InGaZnO Thin‐Film Transistors for Monolithic 3D Capacitor‐Less Dynamic Random Access Memories

P‐1.5: Fabrication of Self‐Aligned Top‐Gate Amorphous InGaZnO Thin‐Film Transistors with Submicron Channel Length

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