An ultrathin atomic-layer-deposited (ALD) AlO x gate insulator (GI) was implemented for self-aligned top-gate (SATG) amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Although the 4.0-nm thick AlO x exhibited ideal insulating properties, the interaction between ALD AlO x and predeposited a-IGZO caused a relatively defective interface, thus giving rise to hysteresis and bias stress instabilities. As analyzed using high-resolution transmission electron microscopy, X-ray photoelectron spectroscopy, and the Hall measurement, the chemical reaction between the ALD precursor and a-IGZO is revealed. This was effectively prevented by preoxidizing a-IGZO with nitrous oxide (N2O) plasma. With 4 nm-AlO x GI and low-defect interfaces, high performance and stability were simultaneously achieved on SATG a-IGZO TFTs, including a near-ideal record-low subthreshold swing of 60.8 mV/dec, a low operation voltage below 0.4 V, a moderate mobility of 13.3 cm2/V·s, a low off-current below 10–13 A, a large on/off ratio over 109, and negligible threshold-voltage shifts less than 0.04 V against various bias-temperature stresses. This work clarifies the vital interfacial reaction between top-gate high-k dielectrics and amorphous oxide semiconductors (AOSs) and further provides a feasible way to remove this obstacle to downscaling SATG AOS TFTs.

No abstract

To strengthen the downscaling potential of top-gate amorphous oxide semiconductor (AOS) 
thin-film transistors (TFTs), the ultra-thin gate insulator (GI) was comparatively implemented using the atomic-layer-deposited (ALD) AlOx and HfOx. Both kinds of high-k GIs exhibit good insulating properties even with the physical thickness thinning to 4 nm. Compared to the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs with 4-nm AlOx GI, the 4-nm HfOx enables a larger GI capacitance, while the HfOx-gated TFT suffers the higher gate leakage current and poorer subthreshold slope, respectively originating from the inherently small band offset and the highly defective interface between a-IGZO and HfOx. Such imperfect a-IGZO/HfOx interface further causes the noticeable positive bias stress (PBS) instability. Both ALD AlOx and HfOx were found to react with the underneath a-IGZO channel to generate the interface defects, such as metal interstitials and oxygen vacancies, while the ALD process of HfOx gives rise to a more severe reduction of a-IGZO. Moreover, when such a defective interface is covered by the top gate, it cannot be readily restored using the conventional oxidizing post-treatments and thus desires the reduction-resistant pre-treatments of AOSs.

No abstract

The capacitor-less embedded dynamic random access memory (eDRAM) based on oxide semiconductor (OS) transistors exhibits a promising future and thus has lead to a growing demand for nanoscale OS thin-film transistors (TFTs). In this work, a self-aligned top-gate (SATG) amorphous InGaZnO (a-IGZO) TFT is demonstrated by using the simplest 3-masks (3M) process, and the downscaling-related issues are carefully addressed to strengthen its back-end-of-line (BEOL) compatibility and mass producibility. The gate insulator (GI) and associated interface defects of the TFTs are jointly optimized with 4-nm atomic-layer-deposited (ALD) AlO x on the pre-oxidized a-IGZO. The defects in a-IGZO channel are further manipulated with a rapid thermal anneal (RTA) in oxygen. By virtue of the strengthened gate controllability and modified channel properties, the fabricated TFT with 97-nm gate length (L g ) exhibits decent performance, such as a maximum on-state current (I ON ) of 32.4 μA μm −1 , as well as clear linear and saturation characteristics. Based on such 3M SATG a-IGZO TFTs with high device performance and inherently minimal parasitic capacitances, the developed capacitor-less eDRAM bit cell achieves a wide sensing margin and a long retention time of over 500 s. A highly manufacturable oxide TFT technology for high-performance and high-density monolithic-3D (M3D) integration is thus well established.