Dramatic increases in latchup holding voltage for sub-0.5 /spl mu/m CMOS using shallow S/D junctions

Abstract

Abstruct-Large increases in the latchup holding voltage are demonstrated with the use of shallow source-drain junctions in a sub-0.5 pm CMOS process. Holding voltages well above the supply voltage for 2 pm n+/p+ spacings are demonstrated without the use of complex processes such as retrograde wells or buried layers. SIMS data is presented to verify the reduction in junction depths to 0.15 pm for the p+/n-well and 0.14 pm for the n+/pwell junction. The improvement in holding voltage is attributed to reductions in parasitic bipolar transistor gains, due to the increase in base width. Well behaved transistor characteristics are presented using the shallow junction technology. / -