Drive current enhancement in p-type metal–oxide–semiconductor field-effect transistors under shear uniaxial stress

Shifren, L.; Wang, X.; Matagne, Philippe; Obradovic, B.; Auth, C.; Cea, S.; Ghani, T.; He, Jianli; Hoffman, T.; Kotlyar, R.; Ma, Zhenqiang; Mistry, K.; Nagisetty, R.; Shaheed, R.; Stettler, M.; Weber, C.; Giles, M.D.

doi:10.1063/1.1841452

Cited by 33 publications

(18 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The data is from [2], Intel bending measurements Under confinement, the ground state subband is heavy-holelike due to the large confinement mass of the heavy-hole band. Its warping and consequent redistribution of carriers in k-space leads to large gains under uniaxial compressive stress on 110 /(100) [20,21]. Additional gain is achieved with increased heavy-light hole splitting due to stress.…”

Section: Stress Physics On (100)mentioning

confidence: 94%

“…17. We use a full band Monte Carlo code with bandstructures computed with the nonlocal EPM method including spin effect [20,21,41]. Average hole mobility and Legend gives substrate doping levels in cm −3 .…”

Section: Stress and Wafer Orientation Physicsmentioning

confidence: 99%

“…Stress physics has been modelled successfully to understand and predict performance gains seen in experiments [3,4,[16][17][18][19][20][21][22][23][24]. The clear connection between the bandstructure changes under stress and mobility gains has been established and discussed.…”

mentioning

confidence: 99%

See 2 more Smart Citations

Modeling the effects of applied stress and wafer orientation in silicon devices: from long channel mobility physics to short channel performance

et al. 2009

Self Cite

View full text Add to dashboard Cite

We review our novel simulation approach to model the effects of applied stress and wafer orientation by mapping detailed dependencies of long channel physics onto short channel device conditions in Silicon NMOS and PMOS. We use kp and Monte Carlo methods to show the long channel dependencies of these effects on gate fields, doping levels, extrinsic charges, and homogeneous driving fields. Our model predicts the reduced effect of wafer orientation on short channel linear and saturation current drives due to weak gate confinement, high carrier density, high stress, and high driving field prevalent in scaled devices. This reduces NMOS (110) wafer orientation loss compared to (100), while keeping PMOS (110) gains over (100) surface orientation in current drives in 110 channels, consistent with data.

show abstract

Section: Stress Physics On (100)mentioning

confidence: 94%

Section: Stress and Wafer Orientation Physicsmentioning

confidence: 99%

See 1 more Smart Citation

Modeling the effects of applied stress and wafer orientation in silicon devices: from long channel mobility physics to short channel performance

et al. 2009

Self Cite

View full text Add to dashboard Cite

show abstract

“…Among them, strained-Si channels were already implemented in the 90 nm technology node and have been regarded as a still quite important technology booster for CMOS under future nodes, where higher strain and combination with multi-gate structures are expected. It has been well recognized that uni-axial compressive strain is quite effective in boosting the hole transport in Si MOS inversion layers [3], which has been explained from the viewpoint of both the effective mass modulation and the band splitting [4][5][6]. As a result, uni-axial strain is also effective in increasing the current drive in short-channel devices.…”

Section: Introductionmentioning

confidence: 99%

High mobility channel CMOS technologies for realizing high performance LSI's

Takagi

2009

2009 IEEE Custom Integrated Circuits Conference

View full text Add to dashboard Cite

Saturation of CMOS performance has been evident in the present 45/32 nm technology node, because of a variety of physical limitations on the miniaturization. Thus, channel engineering, including the enhancement of drive current due to high mobility channel materials and with robustness against short channel effects and characteristic variation due to multi-gate structures, has currently been recognized as mandatory for high performance CMOS. In this paper, we report our approaches to further improvement of MOSFETs by using strained-Si, SiGe, Ge and III-V semiconductor channels on the Si CMOS platform with an emphasis on the combination of ultra-thin body and multi-gate structures. IntroductionThe device scaling concept, which can lead to the increase in both the switching speed and the number density of MOSFETs under reasonable power consumption, had been the main guiding principle of the MOS device engineering over these thirty years. It has been recognized, however, below 32 nm technology node that this conventional device scaling has confronted the difficulty that the three main indices associated with MOSFET performance, on-current, power consumption and short channel effects, have the trade-off relationship with each other, owing to several physical and essential limitations directly related to the device miniaturization, such as tunneling current, mobility reduction, source/drain resistance, inversion-layer capacitance and Sub-threshold slope.Fig. 1 Schematic log I ds -V g characteristics to show the factor affecting power consumption.Fig. 1 shows a schematic Id-Vg curve of MOSFETs.Here, the power consumption, P consum , and the on current, I on , can be roughly described [1] bywhere a, f, C load , I 0 , S, I leak , N s , C g and υ are a constant value, the operating frequency, the load capacitance, the drain current at V g of V th , the Sub-threshold slope, the total leakage current including gate and junction leakages, the induced surface carrier concentration in the channel, the gate capacitance and the velocity near the source region, respectively. In order to realize low power MOSFETs, lower V dd , higher V th , smaller S (higher immunity to short channel effects) and lower I leak are necessary. However, these requirements clearly conflict with high I on , which is still important for signal processing. Also, these requirements pose severe trade-off relationship on choosing device parameters like gate oxides thickness, T ox , substrate impurity concentration, N sub , meaning that it is physically difficult to further improve the performance and power consumption under the conventional Si CMOS scheme. Source Engineering Gate Stack Engineering metal gate high k Channel Engineering SOI Strained Si, Ge, III-V Back gate, Fin Structure, Double gate, Nano-wire etc. Mobility, velocity, ballistic transport Carrier injection velocity Ultra-shallow junction, source resistance, metal S/D Suppression of SCE EOT Inversion-layer thickness Steep impurity profileFig. 2 Schematic diagram of three types of device enginee...

show abstract

“…Bulk Monte Carlo simulations capture the consequences of stress effects on bandstructure, usually treating the inversion physics R. Kotlyar ( ) · C. Weber · L. Shifren · S. Cea · M.D. Giles · M. Stettler Process Technology Modeling, Intel Corporation, 2501 NW 229th Ave., Hillsboro, OR 97124, USA e-mail: roza.kotlyar@intel.com through effective surface models [5]. In previous studies of electron transport in inversion, the effects of inversion anisotropy [6] and band warping [7] under stress have been treated separately.…”

Section: Introductionmentioning

confidence: 99%

Effect of band warping and wafer orientation on NMOS mobility under arbitrary applied stress

et al. 2007

Self Cite

View full text Add to dashboard Cite

We have developed a novel simulation approach to model electron mobility in the inversion layer which encompasses all the important effects of arbitrary wafer and applied stress orientations, such as carrier re-population, band warping, and scattering, going beyond the separate treatments of band warping and inversion anisotropy that have been demonstrated. Our model predicts an important consequence of electron band warping in retaining the increase of stress gain at high stress levels in the presence of shear stress at strong inversion.

show abstract

Drive current enhancement in p-type metal–oxide–semiconductor field-effect transistors under shear uniaxial stress

Cited by 33 publications

References 9 publications

Modeling the effects of applied stress and wafer orientation in silicon devices: from long channel mobility physics to short channel performance

Modeling the effects of applied stress and wafer orientation in silicon devices: from long channel mobility physics to short channel performance

High mobility channel CMOS technologies for realizing high performance LSI's

Effect of band warping and wafer orientation on NMOS mobility under arbitrary applied stress

Contact Info

Product

Resources

About