We review our novel simulation approach to model the effects of applied stress and wafer orientation by mapping detailed dependencies of long channel physics onto short channel device conditions in Silicon NMOS and PMOS. We use kp and Monte Carlo methods to show the long channel dependencies of these effects on gate fields, doping levels, extrinsic charges, and homogeneous driving fields. Our model predicts the reduced effect of wafer orientation on short channel linear and saturation current drives due to weak gate confinement, high carrier density, high stress, and high driving field prevalent in scaled devices. This reduces NMOS (110) wafer orientation loss compared to (100), while keeping PMOS (110) gains over (100) surface orientation in current drives in 110 channels, consistent with data.