A quantitative study of the dynamics of threshold-voltage shifts with time in gallium-indium zinc oxide amorphous thin-film transistors is presented using standard analysis based on the stretched exponential relaxation. For devices using thermal silicon oxide as gate dielectric, the relaxation time is 3 ϫ 10 5 s at room temperature with activation energy of 0.68 eV. These transistors approach the stability of the amorphous silicon transistors. The threshold voltage shift is faster after water vapor exposure suggesting that the origin of this instability is charge trapping at residual-water-related trap sites. © 2009 American Institute of Physics. ͓DOI: 10.1063/1.3187532͔ Amorphous gallium-indium zinc oxide ͑GIZO͒ thin-film transistors ͑TFTs͒ have attracted attention for their possible applications to flat, flexible, and transparent displays, 1-4 especially when processed at low temperatures. However, like the other TFTs' technologies, they also suffer from a stability phenomena known as gate-bias stress. 5,6 This effect manifests itself as a continuous increase in threshold voltage ͑V th ͒ when the gate bias is kept constant over time. This limits the application of these TFTs in demanding applications, such as active matrix organic light emitting displays. The increase in V th lowers the luminance of individual pixels over time, causing display nonuniformity. 7 As an example, using current technologies several driving transistors per pixel are necessary to compensate for the V th shift. Hence, a proper understanding of the stressing mechanism is of paramount importance.Gate-bias stress effects are commonly reported in the literature for a variety of transistors, a-Si TFTs, 8 organic transistors, 9-11 and recently also in amorphous oxide semiconductors TFTs. [12][13][14][15] The effect has been explained as a slow trapping of charge carriers in defects of unknown origin located at the semiconductor/dielectric interface. 13 It is known that the current degradation is faster when the devices are exposed to atmosphere 15,16 and that the stability improves after annealing. 1 Also, it has been reported that the effects can be reduced by the insertion of a passivation layer, either between the dielectric and the semiconductor 17 or on top of the semiconductor in bottom-gate structures. 16 This work provides a quantitative study of the gate-bias stress instability as a function of temperature and environment conditions. The results allow a comparison with competing TFTs technologies. Furthermore, it also provides evidences that water vapor contamination enhances this instability. Therefore, there is no conceptual limitation for the stability of GIZO based TFTs. This is in contrast to hydrogenated amorphous silicon TFTs where the instability is caused by the creation of intrinsic defects, unsaturated valence states into which electrons are trapped.The device fabrication process has been described in detail elsewhere. 18 Briefly, the TFTs were produced with a staggered bottom gate configuration on silicon wafers, which a...