Dual asymmetrical dc voltage source based switched capacitor boost multilevel inverter topology

Siddique, Marif Daula; Mekhilef, Saad; Sarwar, Adil; Alam, Afroz; Shah, Noraisyah Mohamed

doi:10.1049/iet-pel.2019.1567

Cited by 57 publications

(40 citation statements)

References 13 publications

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“…The comparison has been done based on the number of components, voltage stress, voltage gain, and cost function. Based on this table, it can be noted that with asymmetrical configuration, the boosting factor of the proposed topology is higher than the topologies presented in [22] and [27]. It can be noted that the topologies presented in [22], and [27] generated 11 and 13 levels of output voltage using two dc voltage source with asymmetrical configuration, whereas for the proposed topology, 19 levels can be achieved.…”

Section: Comparative Analysismentioning

confidence: 90%

“…It can be noted that the topologies presented in [22], and [27] generated 11 and 13 levels of output voltage using two dc voltage source with asymmetrical configuration, whereas for the proposed topology, 19 levels can be achieved. Further, the topology of [27] higher per unit TSV as compared to the proposed structure. In addition to the component comparison, a cost function (CF) has been defined which has been used to evaluate different topologies of Table IV.…”

Section: Comparative Analysismentioning

confidence: 93%

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A New Family of Step-Up Hybrid Switched-Capacitor Integrated Multilevel Inverter Topologies With Dual Input Voltage Sources

et al. 2021

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Section: Comparative Analysismentioning

confidence: 90%

Section: Comparative Analysismentioning

confidence: 93%

A New Family of Step-Up Hybrid Switched-Capacitor Integrated Multilevel Inverter Topologies With Dual Input Voltage Sources

et al. 2021

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“…Also, the proposed SCMLI1 needs a lower number of DC voltage sources as compared to the CHB inverter and topologies of [9–15, 19, 24]. In the proposed SCMLI1, the switch per level ( N SW / N L ) is 0.8, which is lower than the CHB topology and topologies presented in [12, 14, 16, 17, 19–24]. The topologies presented in [9–11, 13, 14] requires a lower number of switches than the proposed SCMLI1.…”

Section: Comparison Of the Proposed Scmlis With Other Topologiesmentioning

confidence: 99%

“…To address the above drawbacks, the researchers have been focused on switched‐capacitor MLIs (SCMLIs) [16]. These converters featured a less number of switches and less number of DC power supplies, which contributes to reduced weight, volume, and cost [17].…”

Section: Introductionmentioning

confidence: 99%

A multilevel inverter using switched capacitors with reduced components

Taheri

Rasulkhani

Ren

2020

IET power electron.

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In this study, a novel multi‐source switched‐capacitor converter is proposed. In the proposed topology, the capacitor charging is carried out in a self‐balancing form eliminating the need for additional balancing circuits. After that, the design principle of the proposed inverter is discussed in details. A comparison study between the proposed topology and other existing topologies is provided next. According to this comparison, the proposed topology requires fewer components, such as DC power supplies, switches, capacitors, and diodes. Further, the simulation results for 15‐level and 127‐level and the experimental results for a 15‐level inverter are provided. The simulation and experimental results are in close agreement and verify each other.

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“…This topology doesn't require clamping diodes. The features make cascaded H-bridge MLI more preferable over other topologies [21]- [23]. CHB-MLI can have either a symmetrical or asymmetrical structure.…”

Section: Introductionmentioning

confidence: 99%

A Hybrid Nearest Level Combined With PWM Control Strategy: Analysis and Implementation on Cascaded H-Bridge Multilevel Inverter and its Fault Tolerant Topology

Sarwar

Farooqui

et al. 2021

IEEE Access

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This paper presents a hybrid control strategy which combines the nearest level control technique with PWM control technique on a cascaded H-Bridge Multilevel Inverters (MLI). MLIs have become very popular due to its several adavantages in the application areas like industrial drives and gridconnected renewable energy generation systems. With the reduced number of switches, driver circuits, conduction losses, switching losses, voltage stresses, size, and cost of the system, MLI has outperformed its two-level counterpart in terms of power quality issues. Reduction in the Harmonics and consequently the Total Harmonic Distortion (THD) in the output voltage has added to the benefits of MLI. Topological advancements in MLI require a satisfactory output voltage control strategy. In this work, a hybrid control strategy for a smooth and wider range of control of output voltage is proposed. The hybridized scheme enhances the control range of the voltage considerably. Moreover, the THD is also reduced compared to the conventional sinusoidal PWM scheme. A thorough analysis of the scheme has also been presented in the paper. SIMULINK/ MATLAB environment is used for testing the simulation model of the proposed control scheme. This hybridized controlling technique is also simulated for thermal modelling on PLECS software and power loss analysis is performed. The mathematical and simulation analyses are validated on an experimental prototype using a TMS320F28335 DSP controller card. The hybrid scheme has also been tested for a fault tolerant model of the cascaded H-bridge inverter. The performance of the hybrid scheme under different fault condition has also been shown to work satisfactorily.

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Dual asymmetrical dc voltage source based switched capacitor boost multilevel inverter topology

Cited by 57 publications

References 13 publications

A New Family of Step-Up Hybrid Switched-Capacitor Integrated Multilevel Inverter Topologies With Dual Input Voltage Sources

A New Family of Step-Up Hybrid Switched-Capacitor Integrated Multilevel Inverter Topologies With Dual Input Voltage Sources

A multilevel inverter using switched capacitors with reduced components

A Hybrid Nearest Level Combined With PWM Control Strategy: Analysis and Implementation on Cascaded H-Bridge Multilevel Inverter and its Fault Tolerant Topology

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