Dual-Bit/Cell SONOS Flash EEPROMs: Impact of Channel Engineering on Programming Speed and Bit Coupling Effect

Abstract

Abstract-Programming performance of dual-bit silicon-oxidenitride-oxide-silicon memories is studied on cells fabricated using different channel engineering schemes. Both halo and compensation implants are shown to impact the programming speed, bit coupling, and read disturb, and can be suitably adjusted to optimize the cell operation. The doping dependence of bit coupling and the programming speed are verified using well-calibrated 2-D device simulations.Index Terms-Bit coupling, compensation implant, flash, halo implant, localized charge storage, non volatile semiconductor memory (NVSM), program speed, read disturb, SONOS, 2-bit operation.

Multi-level 2-bit/cell operation utilizing Hf-based metal/oxide/nitride/oxide/silicon nonvolatile memory with HfO2 and HfON tunneling layer

“…The read voltage should minimize the disturbance during the read operation for localized programmed states. 31,34) Furthermore, it was reported that high read voltage suppressed the localized charge injection by screening programmed electrons. 34) Thus, the V DS of 1.5 V was utilized as the read voltage to measure the I D -V G of four states of Hf-based MONOS devices with HfO 2 and HfON TL.…”

“…Generally, a CT-type NVM is able to realize the multi-level cell operation utilizing localizedcharge-trapping phenomena. [24][25][26][27][28][29][30][31][32][33][34] Typically, a channel hot electron (CHE) injection into the nitride near the electrode is utilized to localized-charge trapping phenomena. 31,32) Meanwhile, it needs a high drain voltage which causes a high leakage current and high power consumption.…”

A Novel Gate-Assisted Reverse-Read Scheme to Control Bit Coupling and Read Disturb for Multibit/Cell Operation in Deeply Scaled Split-Gate SONOS Flash EEPROM Cells

“…While spatial separation of 2 bit is achievable, bit coupling still remains a concern in [7] that electrostatically resembles a stacked gate cell with isolated charge storage nodes, while in [8], independent control gate (CG) access is needed to make the channel conductive. Recently [9], channel-engineered SONOS cells having a combination of compensation and halo implants were used to optimize bit coupling and read disturb. Such a channel engineering scheme becomes inefficient as incorporation of effec- tive compensation implant dose inside a channel is difficult to control as the channel length scales.…”