Dual Damascene Interconnect Technology for 130-nm-node Complementary Metal–Oxide–Semiconductor Devices Using Ladder-Oxide Film

Yokoyama, Takashi; Shiba, K.; Nishizawa, Atsushi J.; Nagahara, Seiji; Yamato, Hidekazu; Usami, T.; Watanabe, Susumu; Nakabeppu, K.; Kunimune, Yorinobu; Sekine, Makoto; Oda, Noriaki; Horiuchi, T.

doi:10.1143/jjap.42.5543

Cited by 8 publications

(5 citation statements)

References 9 publications

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“…It seemed that the footing was mainly caused because an amine in the low-k film diffused into the resist. 6) An acid in the resist might be neutralized by the amine. We could then improve the resist profile by applying BARC between the resist and the low-k film 3) [Fig.…”

Section: Results and Discussion 221 Improvement By Barcmentioning

confidence: 99%

Application of Electron Projection Lithography to Via Formation in Two-Layer Metallization

Koba¹,

Sakaue²,

Koike³

et al. 2006

jjap

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In this paper we showed electron projection lithography (EPL) applicability to via formation in a back-end-of-line (BEOL) process for 45-nm technology node through fabricating a two-layer metallization device. We developed a single-layer via-resist process for 45-nm technology node. In order to prevent resist profile deteriorations, we optimized process conditions of a bottom anti-reflective coating (BARC) and an electrical conductive film (ECF). As a result, fine 60-nm (1:1) via-patterns were obtained after low-k dry-etching and 67-nm via-holes filling with Cu could be confirmed by using cross-sectional transmission electron microscope (TEM). These results suggested the single-layer via-resist process we developed could be applied for 45-nm technology node. In addition, for 32-nm technology node, we developed a tri-layer via-resist process that had a high resolution compared with a single-layer resist process. There, we could obtain extremely fine 40-nm (1:1) top-layer via-resist patterns. We believe that EPL has high applicability to via formation in BEOL process for not only 45-nm but also 32-nm technology node.

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Section: Results and Discussion 221 Improvement By Barcmentioning

confidence: 99%

Application of Electron Projection Lithography to Via Formation in Two-Layer Metallization

Koba¹,

Sakaue²,

Koike³

et al. 2006

jjap

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“…The formation process of via-holes and upper-metal layer was a modified version of via-first D/D, developed for the previous generations. 22) Compared with the conventional via-first D/D process, 23) chemical-mechanical polishing process to remove the BARC material filled in via-holes was introduced, resulting in a wide focus margin for the upper trench lithography process. The dielectric material is porous SiOC (p-SiOC) with dielectric constant of 2.65, deposited by plasmaenhanced chemical vapor deposition (PECVD).…”

Section: Sample Preparation Processmentioning

confidence: 99%

Fabrication of 70-nm-Pitch Two-Level Interconnects by using Extreme Ultraviolet Lithography

Nakamura¹,

Oda²,

Soda³

et al. 2011

Jpn. J. Appl. Phys.

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We investigate the emissions of atomic potassium excited by two photons near the 4S 1/2 -6S 1/2 transition. Radiation near the 6S 1/2 -4P 3/2,1/2 and 4P 3/2,1/2 -4S 1/2 transitions are studied for the unidirectional and the bidirectional cases, respectively. It is shown that the total output intensity increases considerably for the bidirectional propagation. This is attributed to the effective increase of the Doppler free excitation and the cancellation of the quantum interference effect that is associated with the multiple paths of excitation of certain states.

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“…One is the single-damascene process and the other is the dual-damascene process. 9) To meet the requirement of enhancing the operating speed, it is important to have feasibility in controlling electrical parameters, such as wiring capacitance and resistance. The single-damascene process has such feasibility because via-holes and trench patterns are formed separately and it is easy to change the depths of via-holes and trenches.…”

Section: Single Damascene Cu-plug Structurementioning

confidence: 99%

“…Further studies are necessary to include the dynamic Cu migration effect in the stress simulation. The SIV failure of the D/D structure does not occur when the linewidth is smaller than or equal to 3.0 mm, 9) at which extra vias can be placed. Therefore, the SIV is not a fatal failure for both S/D and D/D structures.…”

Section: Interconnect Reliabilitymentioning

confidence: 99%

A Robust Embedded Ladder-Oxide/Cu Multilevel Interconnect Technology for 0.13 µm Complementary Metal Oxide Semiconductor Generation

Oda

Itô

Takewaki

et al. 2007

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A robust embedded ladder-oxide (k ¼ 2:9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 mm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 mm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO 2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.

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Dual Damascene Interconnect Technology for 130-nm-node Complementary Metal–Oxide–Semiconductor Devices Using Ladder-Oxide Film

Cited by 8 publications

References 9 publications

Application of Electron Projection Lithography to Via Formation in Two-Layer Metallization

Application of Electron Projection Lithography to Via Formation in Two-Layer Metallization

Fabrication of 70-nm-Pitch Two-Level Interconnects by using Extreme Ultraviolet Lithography

A Robust Embedded Ladder-Oxide/Cu Multilevel Interconnect Technology for 0.13 µm Complementary Metal Oxide Semiconductor Generation

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