Dual direction SCR with deep well structure for high voltage ESD in communication bus

Abstract

In order to improve the robustness of the ESD of the dual-direction silicon-controlled rectifier, a low doping deep well PB structure is proposed instead of the traditional high doping P+ structure. The ESD stress of the dual-direction SCR devices with deep well structure is discharged from inside and the lattice temperature of the device is low to avoid premature burnout of the device. The deep well PB structure on the surface of the device increases the parasitic resistance of the device and improve the conduction uniformity of the device. As the main conduction path of the device is located in NBL, the PB structure does not have a large influence on the sustain voltage. It is verified in a 0.25 μm BCD process. With equivalent circuit and two-dimensional device simulation, the working mechanism is analyzed. According to the transmission line pulse test results and comparing with the data from traditional dual-direction SCR structure. The device's fault current increases from 5.486 A to 8.13 A which is suitable for communication bus high voltage electrostatic discharge (ESD) protection.

Dual-directional SCR device with dual-gate controlled mechanism for ESD protection in photoelectric chip

“…Using unidirectional devices for ESD protection results in relatively larger layout area, leading to a significant decrease in robustness per unit area. To address this issue, previous research has proposed dual-directional SCR (DDSCR) ESD protection devices [10][11][12]. However, traditional DDSCR devices have a high V t1 , which cannot guarantee the reliability of the internal circuit's oxide layer.…”

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

“…With the miniaturization of semiconductor feature size and the advancement of integrated circuits, catastrophic ElectroStatic Discharge (ESD) events can seriously deteriorate chip reliability [1][2][3][4][5][6]. Conventional diode structures and Gate-Grounded NMOS (GGNMOS) structures always require a large silicon area to achieve a good ESD robustness [7][8][9][10].…”