Dynamic and Partial FPGA Exploitation

Becker, Juergen; Hübner, Michael; Hettich, Gerhard; Constapel, R.; Eisenmann, J.; Luka, J.

doi:10.1109/jproc.2006.888404

Cited by 115 publications

(60 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Therefore, it is needed to find alternative system architectures able to meet both key requirements: high performance and low cost. advantage and exploits the dynamic reconfigurability performance of FPGAs (Becker et al, 2007) in the physical implementation of a complete personal recognition application based on biometrics. Time-to-market pressures and cost constraints are pushing embedded systems to new levels of flexibility and system integration.…”

Section: Proof Of Concept I: Software-only Implementationmentioning

confidence: 99%

Exploiting run-time reconfigurable hardware in the development of automatic fingerprint-based personal recognition applications

Fons¹,

Fons²

2011

Recent Application in Biometrics

View full text Add to dashboard Cite

Section: Proof Of Concept I: Software-only Implementationmentioning

confidence: 99%

Exploiting run-time reconfigurable hardware in the development of automatic fingerprint-based personal recognition applications

Fons¹,

Fons²

2011

Recent Application in Biometrics

View full text Add to dashboard Cite

“…In data intensive applications, a large amount of data needs to be transferred from core to core. Therefore, data communication is usually a primary anticipated bottleneck for system performance [Altera, 2008;Becker et al, 2007;Donchev et al, 2006;Kavadias et al, 2010]. One important method to improve the performance of such systems is reducing data communication overhead.…”

Section: Introductionmentioning

confidence: 99%

“…Examples of the former are [Altera, 2008;Becker et al, 2007;Donchev et al, 2006;Jackson and Hollis, 2010;Stensgaard and Sparso, 2008] and of the latter are [Kavadias et al, 2010;Papaefstathiou et al, 2007]. However, all the aforementioned works are based on static information of the application such as task graphs.…”

Section: Introductionmentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

View full text Add to dashboard Cite

Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and are thus more energy efficient and have higher performance than general purpose processors, while still providing a large degree of flexibility. However, system performance dose not scale when increasing the number of processing cores due to the communication overhead which increases greatly with the increasing number of cores. Although data communication is a primary anticipated bottleneck for system performance, the interconnect design for data communication among the accelerator kernels has not been well addressed in hardware accelerator systems. A simple bus or shared memory is usually used for data communication between the accelerator kernels. In this dissertation, we address the issue of interconnect design for heterogeneous hardware accelerator systems.Evidently, there are dependencies among computations, since data produced by one kernel may be needed by another kernel. Data communication patterns can be specific for each application and could lead to different types of interconnect. In this dissertation, we use detailed data communication profiling to design an optimized hybrid interconnect that provides the most appropriate support for the communication pattern inside an application while keeping the hardware resource usage for the interconnect minimal. Firstly, we propose a heuristicbased approach that takes application data communication profiling into account to design a hardware accelerator system with a custom interconnect. A number of solutions are considered including crossbar-based shared local memory, direct memory access (DMA) supporting parallel processing, local buffers, and hardware duplication. This approach is mainly useful for embedded system where the hardware resources are limited. Secondly, we propose an automated hybrid interconnect design using data communication profiling to define an optimized interconnect for accelerator kernels of a generic hardware accelerator system. The hybrid interconnect consists of a network-on-chip (NoC), vii viii ABSTRACT shared local memory, or both. To minimize hardware resource usage for the hybrid interconnect, we also propose an adaptive mapping algorithm to connect the computing kernels and their local memories to the proposed hybrid interconnect. Thirdly, we propose a hardware accelerator architecture to support streaming image processing. In all presented approaches, we implement the approach using a number of benchmarks on relevant reconfigurable platforms to show their effectiveness. The experimental results show that our approaches not only improve system performance but also reduce overall energy consumption compared to the baseline systems.

show abstract

“…In this paper, the Dynamic and Partial Reconfiguration (DPR) of commercial Xilinx FPGAs is leveraged [1] [2]. DPR allows the design of IP cores offering run-time adaptable parallelism, and achieving a flexible assignment of resources.…”

Section: Introductionmentioning

confidence: 99%

Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs

Otero¹,

Torre²,

Riesgo³

et al. 2011

2011 21st International Conference on Field Programmable Logic and Applications

View full text Add to dashboard Cite

Abstract-Systems relying on fixed hardware components with a static level of parallelism can suffer from an underuse of logical resources, since they have to be designed for the worst-case scenario. This problem is especially important in video applications due to the emergence of new flexible standards, like Scalable Video Coding (SVC), which offer several levels of scalability.In this paper, Dynamic and Partial Reconfiguration (DPR) of modern FPGAs is used to achieve run-time variable parallelism, by using scalable architectures where the size can be adapted at run-time. Based on this proposal, a scalable Deblocking Filter core (DF), compliant with the H.264/AVC and SVC standards has been designed. This scalable DF allows run-time addition or removal of computational units working in parallel. Scalability is offered together with a scalable parallelization strategy at the macroblock (MB) level, such that when the size of the architecture changes, MB filtering order is modified accordingly.

show abstract

Dynamic and Partial FPGA Exploitation

Cited by 115 publications

References 12 publications

Exploiting run-time reconfigurable hardware in the development of automatic fingerprint-based personal recognition applications

Exploiting run-time reconfigurable hardware in the development of automatic fingerprint-based personal recognition applications

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs

Contact Info

Product

Resources

About