2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014 2014
DOI: 10.1109/apec.2014.6803502
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Dynamic and static behavior of packaged silicon carbide MOSFETs in paralleled applications

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Cited by 108 publications
(45 citation statements)
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“…The effectiveness of this particular TSEP should be studied for each MOSFET, especially given the different generations available on the market [7]. This also includes the study of the variability of the on-state resistance for devices of the same technology but different process batches.…”
Section: Discussion On Condition Monitoring and Additional Consideratmentioning
confidence: 99%
See 1 more Smart Citation
“…The effectiveness of this particular TSEP should be studied for each MOSFET, especially given the different generations available on the market [7]. This also includes the study of the variability of the on-state resistance for devices of the same technology but different process batches.…”
Section: Discussion On Condition Monitoring and Additional Consideratmentioning
confidence: 99%
“…The gate voltage V GS applied to turn-on the device affects the value of the resistance. This is a well-known fact and is one of the reasons why SiC MOSFETs require a high gate voltage in order to properly invert the channel and obtain a low on-state resistance compared with silicon MOSFETs [6,7], as well as avoiding a negative temperature coefficient, which can cause thermal runaway in case of paralleled devices.…”
Section: Mosfet On-state Resistance Analysismentioning
confidence: 99%
“…This fact makes condition monitoring of SiC MOSFETs using TSEPs a challenging task. The temperature dependency of the on-state resistance in SiC is not linear [24] and is low. Fig.…”
Section: Introductionmentioning
confidence: 99%
“…As indicated by Equation 4 and Equation 6, bus bar stray inductances in phases U and W can be made equal in the double-sided structure. In addition, comparing Equation 2 and Equation 5, V-phase bus bar stray inductance can be reduced in the double-sided structure so that lower values of bus bar stray inductance can be adopted in design.…”
Section: Proposal Of Circuit Structurementioning
confidence: 99%
“…In so doing, heat dissipation of the power modules must be equalized, and switching loss balancing is a key issue. In this context, a number of studies deal with parallel connection of power modules; thus, influence of characteristics of semiconductor devices was examined, 6 and a method was proposed to reduce switching loss imbalance by improving gate drive circuits. 7,8 In addition, effects of DC-side stray inductance are also reported; particularly, reducing variation of DC-side stray inductance proves effective to suppress switching loss imbalance.…”
Section: Introductionmentioning
confidence: 99%