Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures

Hajimiri, Hadi; Mishra, Prabhat; Bhunia, Swarup

doi:10.1109/vlsid.2013.161

Cited by 8 publications

(4 citation statements)

References 8 publications

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“…Compared to the baseline (7), heterogeneous configurations present up to 90% better performance, while spend up to 50% more energy. Comparing performance versus energy ratio, as shown in Figure 8b, we observe that configurations (6), (10), and (16) present the largest ratios. As a consequence, these latter configurations are the most interesting when a shutdown operation of parts of L2 cache is applied on (8) or an activation of these parts on (20).…”

Section: ) Performance and Energymentioning

confidence: 84%

“…In the report [10], Hajimiri et al present a genetic algorithm that is able to propose an efficient dynamic cache reconfiguration and its partition aiming performance and energy efficiency. Our approach is designed to be employed by a designer to assist the In the report by Kotera [12], a cache mechanism composed of way-allocation function and a power control function both based on the cache locality assessment is proposed.…”

Section: Related Workmentioning

confidence: 99%

“…For example, energy [2][15] [16], performance [2][15] [16][17], energy over performance, combination of the previous using a bio-inspired algorithm [10]. Previous works published were mostly concerned to the fundamental aspects of performance and power, which can hide the exposition of computer architectural design aspects' behavior to the designer.…”

Section: Introductionmentioning

confidence: 99%

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Last level cache size heterogeneity in embedded systems

Marino

2016

J Supercomput

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In typical multicore processors, Last Level Caches (LLC) are formed by distributed clusters of memory banks of the same size, namely homogeneous ones. By shutting down part of these clusters to save power along generations of multicore processors, clusters with non homogeneous cache sizes can be originated, named as heterogeneous ones. Given that heterogeneous clusters have typically smaller sizes than homogeneous ones, they present larger miss rates that are likely to deteriorate performance.In this investigation, we study the impact of heterogeneous caches in embedded microprocessors, by having an arbitrary mix of homogeneous and heterogeneous clusters. That is, we propose to evaluate the architectural implications of these heterogeneous caches and a flexible algorithm that can be used to explore them. From scientific applications' experimental benchmarking, our findings show that microprocessors with heterogeneous clusters present a maximal performance degradation of about 10% and maximal performance improvement of 16%, while obtaining maximum miss hit rate of reduction and improvement up to 10%. In addition, 10% of coherence activity decrease when presenting maximum energy utilization up to 50% and maximum energy reduction of 15%.

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Section: ) Performance and Energymentioning

confidence: 84%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Last level cache size heterogeneity in embedded systems

Marino

2016

J Supercomput

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“…This cache architecture can achieve up to 40% energy saving, but which cannot guarantee the strict cache isolation among real-time applications. In Hajimiri et al, 14 inter-task dynamic cache reconfiguration (DCR) technique has been proposed to reduce the contention and optimize energy consumption of the cache in real-time systems. In Mittal et al, 15 a multicore cache energy saving technique using dynamic cache reconfiguration was proposed to save cache energy by periodically allocating suitable amount of cache space to each running programs.…”

Section: Reconfigurable Cachementioning

confidence: 99%

Worst-case energy consumption minimization based on interference analysis and bank mapping in multicore systems

Gan

Tan

et al. 2017

International Journal of Distributed Sensor Networks

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Energy is a scarce resource in real-time embedded systems due to the fact that most of them run on batteries. Hence, the designers should ensure that the energy constraints are satisfied in addition to the deadline constraints. This necessitates the consideration of the impact of the interference due to shared, low-level hardware resources such as the cache on the worst-case energy consumption of the tasks. Toward this aim, this article proposes a fine-grained approach to analyze the bank-level interference (bank conflict and bus access interference) on real-time multicore systems, which can reasonably estimate runtime interferences in shared cache and yield tighter worst-case energy consumption. In addition, we develop a bank-to-core mapping algorithm for reducing bank-level interference and improving the worst-case energy consumption. The experimental results demonstrate that our approach can improve the tightness of worst-case energy consumption by 14.25% on average compared to upper-bound delay approach. The bank-to-core mapping provides significant benefits in worst-case energy consumption reduction with 7.23%.

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