Dynamic Characteristics of Power Gating During Mode Transition

Xu, Haoyang; Vemuri, Ranga; Jone, Wen-Ben

doi:10.1109/tvlsi.2009.2033699

Cited by 20 publications

(7 citation statements)

References 25 publications

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“…In power gating scheme, the leakage currents are almost minimized by introducing the external header and footer transistors. These transistors eliminate the path exiting between V DD to ground when the devices are in quiescent mode [77] [78].…”

Section: Power Gating Techniquesmentioning

confidence: 99%

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Bikki¹,

Karuppanan²

2017

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Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.

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Section: Power Gating Techniquesmentioning

confidence: 99%

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Bikki¹,

Karuppanan²

2017

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“…In [5] and [11], a need for wakeup latency estimation arises to quantify the effectiveness of proposed ground-bounce reducing techniques and intermediate strength power gating techniques respectively under a wakeup time constraint. In [14], Xu et al have proposed numerical approaches for estimation of as a function of time in sleep mode. To extend the same method to wakeup mode, it is necessary to incorporate size dependent sleep transistor current characteristics.…”

Section: Related Workmentioning

confidence: 99%

“…In [14], compact models for leakage current have been derived at gate and circuit levels in a hierarchical way. It was shown that the leakage current can be represented by a voltage controlled current source (VCCS) as in Fig.…”

Section: Power-gated Logic Cluster Modelmentioning

confidence: 99%

A semiempirical model for wakeup time estimation in power-gated logic clusters

Tovinakere

Sentieys

Derrien

2012

Proceedings of the 49th Annual Design Automation Conference

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Wakeup time is an important overhead that must be determined for effective power gating, particularly in logic clusters that undergo frequent mode transitions for run-time leakage power reduction. In this paper, a semiempirical model for virtual supply voltage in terms of basic parameters of the power-gated circuit is presented. Hence a closed-form expression for estimation of wakeup time of a power-gated logic cluster is derived. Experimental results of application of the model to ISCAS85 benchmark circuits show that wakeup time may be estimated within an average error of 16.3% across 22× variation in sleep transistor sizes and 13× variation in circuit sizes with significant speedup in computation time compared to SPICE level circuit simulations.

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“…An automated gate biasing technique has been developed to determine the gate bias voltage which minimizes leakage current [8]. Power gating characterization at early stages of the design process has been proposed [9]. Novel power gating approaches that utilize nano-electro-mechanical power switches with zero leakage current (off state) rather than MOS power switches have been examined [10].…”

Section: Introductionmentioning

confidence: 99%

Adaptive power gating of 32-bit Kogge Stone adder

et al. 2016

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Static power consumes a significant portion of the available power budget. Consequently, leakage current reduction techniques such as power gating have become necessary. Standard global power gating approaches are an effective method to reduce idle leakage current, however, global power gating does not consider partially idle circuits and imposes significant delay and routing constraints. An adaptive power gating technique is applied locally to a 32-bit Kogge Stone adder, and evaluated at the 16 nm FinFET technology node. This high granularity adaptive power gating approach employs a local controller to lower energy use and reduce circuit overhead. The controller conserves additional power when the circuit is partially idle (based on the inputs to the adder) by adaptively powering down inactive blocks. Moreover, the local controller reduces routing complexity since a global power gating signal is not required. The proposed adaptive power gating technique exhibits significant energy savings, ranging from 8% to 21%. This technique targets partially idle circuits, and therefore complements rather than replaces global power gating techniques. A 12% delay overhead results in a 5% area overhead. This delay overhead is reduced to 5% by increasing the area overhead to 16%, and can be further reduced by trading off additional area.

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Dynamic Characteristics of Power Gating During Mode Transition

Cited by 20 publications

References 25 publications

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

A semiempirical model for wakeup time estimation in power-gated logic clusters

Adaptive power gating of 32-bit Kogge Stone adder

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