Adaptive power gating of 32-bit Kogge Stone adder

Shapiro, Alexander E.; Atallah, Francois; Kim, Kyugseok; Jeong, Jihoon; Fischer, Jeff; Friedman, Eby G.

doi:10.1016/j.vlsi.2015.12.001

Cited by 8 publications

(3 citation statements)

References 11 publications

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“…The important aim is to examine the trade-off between area consumption delay and power consumption in the particular PPA depends upon the design performance. All the designs are using a power gating technique to reduce the power consumption [15].…”

Section: Design and Analysis Of Proposed 32 Bit Various Ppamentioning

confidence: 99%

Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications

Daphni¹,

Grace²

2019

Adv. sci. technol. eng. syst. j.

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The basic processes like addition, subtraction can be done using various types of binary adders with dissimilar addition times (delay), area and power consumption in any digital processing applications. To minimize the Power Delay Product (PDP) of Digital Signal Processing (DSP) processors is necessary for high performance in Very Large Scale Integration (VLSI) applications. In this paper, a 32-bit various Parallel Prefix adders design is proposed and compared the performance results on the aspects of area, delay and power. Implementation (Simulation and Synthesis) results really achieve significant improvement in power and power-delay product when compared with the previous bit adders which is used in processors. To reduce the power, here apply the energy recovery logic like power gating technique for all three adders. All the simulations and synthesis results can be noted using Xilinx ISE 14.2i tool.

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Section: Design and Analysis Of Proposed 32 Bit Various Ppamentioning

confidence: 99%

Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications

Daphni¹,

Grace²

2019

Adv. sci. technol. eng. syst. j.

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“…Power gating technique has been proposed for the recent technologies (Xu et al, 2011). KSA was also developed using adaptive gating technique (Shapiro et al, 2016). The delay of the reported KSA was very less,but the area occupied was more and there was a need of trade-off between delay and area.…”

Section: Introductionmentioning

confidence: 99%

Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process

John

Sam

Radha

et al. 2020

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Purpose The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V. Design/methodology/approach In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates. Findings The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. Originality/value In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.

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“…Only one relevant core is active at a time to perform scheduled tasks with higher energy efficiency, while the other core is power gated. 7 This solution, however, requires significant area overhead and complex synchronization between the cores.…”

Section: Introductionmentioning

confidence: 99%

Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies

Shapiro¹,

Friedman²

2017

Journal of Low Power Electronics

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Energy efficiency has been a primary focus over the past decade. Energy saving techniques such as dynamic voltage and frequency scaling, power gating, and many-core systems-on-chip, have been extensively studied. These techniques, however, struggle to deliver desired energy efficiencies while failing to exploit wide supply voltage ranges in mobile sub-22 nm microprocessors. Additionally, scaling exacerbates these problems, resulting in significant parasitic interconnect resistances. A major factor that limits dynamic wide voltage ranges and frequency scaling is the inability to optimize interconnect to support a wide voltage range from nominal to subthreshold voltages. The primary contribution of this work is the analysis and optimization of repeater insertion for wide supply voltage range applications. A closed-form delay model supporting wide voltage ranges is developed to enable this analysis. The model supports an ultra-wide voltage range from nominal voltages to deep subthreshold voltages, and repeater size multipliers up to 640 times the minimal size. The model is validated with SPICE using a commercial 14 nm FinFET transistor model for interconnect resistances and capacitances up to, respectively, 2 k and 2 pF. The model exhibits good accuracy across the entire parameter space, with the worst case error ranging from −3.5% to 7.3% (−12% to 13% in the subthreshold region) for single stage delays, and from −17% to 9% (−15% to 17% in the subthreshold region) for long interconnect lines with repeaters. Challenges to repeater insertion are also evaluated based on the proposed model.

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Adaptive power gating of 32-bit Kogge Stone adder

Cited by 8 publications

References 11 publications

Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications

Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications

Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process

Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies

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