Dynamic scheduling of task graphs in multi-FPGA systems using critical path

Ramezani, Reza

doi:10.1007/s11227-020-03281-3

Cited by 12 publications

(4 citation statements)

References 31 publications

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“…Moreover, hardware-application matching can serve as an enabler for simultaneous execution of small tasks by assigning portions of available hardware to each task [35]. In multi-FPGA environments, dynamic scheduling assigns priority to tasks in diferent steps to achieve optimal makespans [41].…”

Section: Virtualization Of the Reconfigurable Optical Computer (Roc)mentioning

confidence: 99%

Virtualizing a Post-Moore’s Law Analog Mesh Processor: The Case of a Photonic PDE Accelerator

Anderson

Kayraklioglu

Imani

et al. 2023

ACM Trans. Embed. Comput. Syst.

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Innovative processor architectures aim to play a critical role in future sustainment of performance improvements under severe limitations imposed by the end of Moore’s Law. The Reconfigurable Optical Computer (ROC) is one such innovative, Post-Moore’s Law processor. ROC is designed to solve partial differential equations in one shot as opposed to existing solutions, which are based on costly iterative computations. This is achieved by leveraging physical properties of a mesh of optical components that behave analogously to lumped electrical components. However, virtualization is required to combat shortfalls of the accelerator hardware. Namely, 1) the infeasibility of building large photonic arrays to accommodate arbitrarily large problems, and 2) underutilization brought about by mismatches in problem and accelerator mesh sizes due to future advances in manufacturing technology. In this work, we introduce an architecture and methodology for light-weight virtualization of ROC which exploits advantages borne from optical computing technology. Specifically, we apply temporal and spatial virtualization to ROC and then extend the accelerator scheduling tradespace with the introduction of spectral virtualization. Additionally, we investigate multiple resource scheduling strategies for a system-on-chip (SoC)-based PDE acceleration architecture and show that virtual configuration management offers a speedup of approximately 2 ×. Finally, we show that overhead from virtualization is minimal, and our experimental results show two orders of magnitude increased speed as compared to microprocessor execution while keeping errors due to virtualization under 10%.

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Section: Virtualization Of the Reconfigurable Optical Computer (Roc)mentioning

confidence: 99%

Virtualizing a Post-Moore’s Law Analog Mesh Processor: The Case of a Photonic PDE Accelerator

Anderson

Kayraklioglu

Imani

et al. 2023

ACM Trans. Embed. Comput. Syst.

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“…The cluster scheduling can increase processor utilization; reduce scheduling and other overheads by controlling the size of the cluster. Different types of clusters can be form based on high and low utilization of tasks 43 . Another flexibility offered by the clustering is to create a cluster with different resource capabilities.…”

Section: Related Workmentioning

confidence: 99%

Cluster formation techniques for hierarchical real time tasks allocation on multiprocessor system

Talmale

Shrawankar

2021

Concurrency and Computation

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Summary Real‐time systems are nowadays extensively used in most time‐critical embedded applications. The existing multiprocessor real‐time scheduling algorithms are based on partitioned and global scheduling approaches. The partitioned‐based algorithms suffer poor utilization bound, load balancing, not compatible for an open system environment, and the global scheduling approach faces problems like high scheduling, migration overhead. Cluster scheduling represents a hybrid scheduling approach which consists of a set of processors as clusters and tasks scheduled to each processor of clusters using a global scheduling approach. The different cluster formation heuristics are investigated for homogenous clusters. The main objective of this article is to propose task utilization‐based cluster formation and harmonic period aware task allocation for a hierarchical real‐time system on a multiprocessor platform. Tasks with high utilization, cluster size tune to a smaller value to achieve high utilization. Tasks with low utilization, the size of cluster tune to larger to reduce migration and scheduling overheads. Experimentation performed on multiprocessor real‐time simulator with a different set of tasks, multiprocessor system, different tasks utilization, and cluster size. Simulation results show that cluster base approach increases the number of tasks scheduled on a multiprocessor system, system utilization, and reduces response time, migration, and preemption overheads.

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“…Typically, in modern FPGAs, a single basic element is not the minimum addressable segment of the device that can be reconfigured separately. Instead, a set of them must be reconfigured at the same time, which in this paper is referred to as the CLB group [24]. Thus, the target SRAM-based FPGA 𝑆𝐹 is modeled as:…”

Section: B) Partially Run-time Reconfigurable Fpga Modelmentioning

confidence: 99%

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

Ramezani

Clemente

Franco

2020

Reliability Engineering & System Safety

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Dynamic scheduling of task graphs in multi-FPGA systems using critical path

Cited by 12 publications

References 31 publications

Virtualizing a Post-Moore’s Law Analog Mesh Processor: The Case of a Photonic PDE Accelerator

Virtualizing a Post-Moore’s Law Analog Mesh Processor: The Case of a Photonic PDE Accelerator

Cluster formation techniques for hierarchical real time tasks allocation on multiprocessor system

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

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