Dynamic through-silicon-via filling process using copper electrochemical deposition at different current densities

Abstract

This work demonstrates the dynamic through-silicon-via (TSV) filling process through staged electrodeposition experiments at different current densities. Different morphologies corresponding to TSV filling results can be obtained by controlling the applied current density. Specifically, a low current density (4 mA/cm2) induces seam defect filling, a medium current density (7 mA/cm2) induces defect-free filling, and a high current density (10 mA/cm2) induces void defect filling. Analysis of the filling coefficient indicates that the effect of current density on the TSV filling models is triggered by the coupling effect of consumption and diffusion of additives and copper ions. Further, the morphological evolution of plating reveals that the local deposition rate is affected by the geometrical characteristics of the plating.

Controlling Interfacial Ion-Transport Kinetics Using Polyelectrolyte Membranes for Additive- and Effluent-free, High-Performance Electrodeposition

“…Such a setup requires large-volume deposition baths with high concentrations of chemical reagents that produce large amounts of effluent. The current maximum deposition rate, for instance, for the fabrication of copper in a printed circuit board or in a silicon-via-filling process, is relatively small (∼0.1–1.5 μm min –1 at 30–40 °C) using such complex baths. ,, Therefore, high-performance, area-selective deposition processes that enable the direct deposition of metal patterns at high rates using small-volume baths at low concentrations need to be developed to overcome these restrictions; they would also strongly impact on the abovementioned environmental and energy-related issues.…”

Warpage Behavior on Silicon Semiconductor Device: The Impact of Thick Copper Metallization

“…Furthermore, Cu metallization is better than aluminum in terms of resistance to electromigration and stress voiding phenomena [3,4]. The main technique to produce thick copper film on silicon substrate is electrochemical deposition (ECD), which is a highly efficient wet process for depositing a uniform layer of metal (like copper) on a semiconductor wafer [5,6]. Furthermore, Cu front metal is very attractive for integrated circuit (IC) manufacturing because it enables high-reliable Cu-Cu wire bonding solution [7][8][9][10].…”

Effect of Pulsed Light Irradiation on Patterning of Reduction Graphene Oxide-Graphene Oxide Interconnects for Power Devices

“…In recent years, decreasing the through silicon via (TSV) size has caused a rapid increase in the aspect ratio (AR) during pitching in technology nodes below 10 nm [1], resulting in poor film coverage of barrier/seed layers owing to thermomechanical stress [2]. Problematic resistance (R)-capacitance (C) delays with increased resistance caused the boundary scattering and shorter mean free paths that result from using nano-thick copper as a reasonable material for interconnections [3][4][5].…”