Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application

Analog Integr Circ Sig Process

2009

The deep sub-micron (DSM) process nodes are increasingly marred by layout-dependent effects. The principal reason preventing layout synthesis during circuit design is the cost of edition, verification and extraction of the intermediate solutions repeatedly. This paper proposes a circuit and layout co-optimization scheme through a novel parasitic model-building scheme that exchanges information between the two flows. A placement-based parasitic estimation method to provide parasitic estimations to schematic optimization tools while retaining their efficiency. Extracted parasitics and simulated performance data are imparted into parasitic macro-devices and performance sensitivities. As proved by experimental results, the flexibility of the parasitic models bridges the efficiency and accuracy void between schematic and physical design optimization to ensure rapid DSM design closure.

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“…Recently proposed automated analog cell generation [12] and placement tools [13][14][15] are driven by geometric constraints. Parasitic considerations are ignored until postextraction.…”

Section: Performance-driven Layout Optimizationmentioning

confidence: 99%

“…Empirical optimizers based on evolutionary and annealing-based optimization schemes are often used to efficiently cover non-linear performance spaces efficiently. In [14], random placement candidates are generated. The best candidates determined by some objective functions are saved.…”

Section: Performance-driven Layout Optimizationmentioning

confidence: 99%

Performance-driven circuit and layout co-optimization for deep-submicron analog circuits

Analog Integr Circ Sig Process

2009

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“…In [5], random placement candidates are generated. The best candidates determined by some objective functions are saved.…”

Section: Topological Placement Optimizationmentioning

confidence: 99%

Parasitic-aware physical design optimization of deep sub-micron analog circuits

2007 50th Midwest Symposium on Circuits and Systems

2007

Performance, versatility, portability and reliability are common goals of robust designs. In deep sub-micron technologies, these goals often contain contradicting objectives only revealed at the physical design level. Design objectives often cannot be effectively satisfied without exploring detailed trade-offs. Well-performing schematic designs can hence only be realized if followed-through with a quality-based physical design flow. We present a performance-driven physical design algorithm to optimize custom analog circuits containing guard bands in mixed-signal environment. Parasitic effects are minimized under symmetry, matching and displacement constraints while preserving the customized layout topology.

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A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

2007