Successful deep-submicron designs require significant computation resources for thorough signal and design integrity analysis. Rising quality expectations and shortening time-to-market requirements present additional challenges for design closure. Conventional analog circuit optimizers are efficient in circuit analysis and optimization. Due to recent promising results, designers begin to adopt automated physical synthesis in their condensed development cycles in order to improve their prototyping efficiency. For high-performance circuits optimization, idealized performance as well as parasitic data should also be considered. This paper presents an effective framework to incorporate parasitic effects into a sensitivity-based circuit optimization tool. To relieve the physical synthesis bottleneck, estimations of parasitic values based on past extraction results are made during incremental design changes. Sensitivities of the performance impact can then be computed efficiently. As a result physical performance can be optimized using available optimizer and synthesis tools without the need of a priori expert rules, knowledge or cell libraries.

Wormhole routed mesh networks can suffer from blocking due to contention when multiple packets are routed along the same path. This paper presents a new method that accounts for blocking and assigns tasks to nodes in a way that tries to minimize contention and thus reduce the latencies introduced by blocking using simulated annealing. We have implemented a xy routed wormhole mesh in SystemC that enables us to evaluate the effectiveness of our methodology. Results show that our methodology is effective at reducing blocking costs and latencies when compared to minimizing communication distances only.

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The deep sub-micron (DSM) process nodes are increasingly marred by layout-dependent effects. The principal reason preventing layout synthesis during circuit design is the cost of edition, verification and extraction of the intermediate solutions repeatedly. This paper proposes a circuit and layout co-optimization scheme through a novel parasitic model-building scheme that exchanges information between the two flows. A placement-based parasitic estimation method to provide parasitic estimations to schematic optimization tools while retaining their efficiency. Extracted parasitics and simulated performance data are imparted into parasitic macro-devices and performance sensitivities. As proved by experimental results, the flexibility of the parasitic models bridges the efficiency and accuracy void between schematic and physical design optimization to ensure rapid DSM design closure.